pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 125

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
4.0 Embedded Controller Modules
The auxiliary device then completes the transfer by sending the line-control bit. The line-control bit, is identified by the data
signal being low after the 11th falling edge of the clock.
End of Transmission
The End-Of-Transmission state is entered when the line-control bit is detected. In response, the shift mechanism holds all
clock signals low, and if the internal pull-up is enabled, all data signals are pulled high by the internal pull-up.
The End-Of-Transaction flag (EOT in PSTAT register) is set to indicate that the transmit operation was completed; in addi-
tion, if EOTIE bit in PSIEN register is set, the interrupt signal to the ICU is set high.
The shift mechanism stays at this state until being reset.
Figure 42 shows the transmit byte sequence, as defined by the PS/2 standard.
Transfer Abort
At each stage of a receive or transmit operation, the transaction can be aborted by clearing all four channel enable bits
(CLK4-1) in PS/2 Output Signal register (PSOSIG) to 0. This resets the shifter state machine and puts it in the Enabled In-
active state. If the shift mechanism is in Transmit Inactive or Transmit Idle state, WDAT4-1 bits should also be set.
4.6.5
For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 32.
PS/2 Register Map
PS/2 Interface Registers
CLK
DATA
PSDAT
PSTAT
PSCON
PSOSIG
PSISIG
PSIEN
Mnemonic
Inhibit
I/O
Start Bit
PS/2 Data Register
PS/2 Status Register
PS/2 Control Register
PS/2 Output Signal Register
PS/2 Input Signal Register
PS/2 Interrupt Enable Register
Figure 42. PS/2 Transmit Data Byte Timing
CLK
1st
Bit 0
(Continued)
Register Name
CLK
2nd
125
CLK
9th
Parity Bit
10th
CLK
Stop Bit
Type
R/W
R/W
R/W
R/W
RO
RO
CLK
11th
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