pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 119

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
4.0 Embedded Controller Modules
4.6
The PS/2 protocol is an industry-standard, PC-AT-compatible interface for keyboards. It uses a two-wire bidirectional TTL
interface for data transmission. Several vendors also supply PS/2 mouse products and other pointing devices that employ
the same type of interface.
The PC87591L-N05 provides four PS/2 data transfer channels. Each channel has two quasi-bidirectional signals that serve
as direct interfaces to an external keyboard, mouse or any other PS/2-compatible pointing device. Since the four channels
are identical, the connector ports are interchangeable.
4.6.1
4.6.2
In the previous generation of keyboard controllers, firmware executed the PS/2 device interface by toggling the interface
signals. The PC87591L-N05 supports this bit toggling mode via either polling or interrupt-driven clock edge detection.
PS/2 devices’ firmware is significantly simplified through the use of a hardware accelerator mechanism. The accelerator in-
cludes an 8-bit shift register, a state-machine and control logic that handle both the incoming and outgoing data. It reduces
code overhead, performance requirements and reduces the overall interrupt latency from the core firmware. The hardware
is designed to meet the PS/2 device interface as defined in Keyboard and Auxiliary Device Controller (Types 1 and 2),
August 1988.
Section Naming conventions
Interface Signals
The PS/2 interface includes eight external signals (PSCLK4-1 and PSDAT4-1) and six registers.
Module Block Diagram
A schematic description of the PS/2 interface appears in Figure 37. The interface to the three channels is symmetric and
only channel 1 is detailed in the figure.
• Four PS/2 channels
• Enable/Disable for each of the four channels
• Automatic hardware shift mechanism
• Hardware support for PS/2 auxiliary device protocol
• Processor interrupts at the beginning and end of data transfer
• Optional software-based PS/2 implementation
• In this section, the term “channel” describes the interface to one of the PS/2 devices and its two associated signals
• The term “shift mechanism” refers to the hardware accelerator.
• The term “PS/2 interface” refers to the entire mechanism.
(clock and data).
PS/2 INTERFACE
Features
General Description
PS/2 I/F
Registers
RCLK1
WDAT1
RDAT1
CLK1
ENSM
Channel 1
Channel 2
EN1
Channel 3
EN2
Channel 4
Figure 37. PS/2 Interface Functional Diagram
EN3
EN4
DATI1
DATI2
DATI3
DATI4
(Continued)
DATO1
DATO2
DATO3
Shift Mechanism
DATO4
119
CLKI1
CLKI2
CLKI3
CLKI4
CLKO1
CLKO2
CLKO3
CLKO4
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PSDAT1
PSCLK1