pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 26

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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1.0 Introduction
1.3.1
The CompactRISC CR16B core (referred to in this datasheet as the “core”) is an advanced, general-purpose 16-bit micropro-
cessor core with a RISC architecture. The core is responsible for arithmetic and logic operations, as well as program control.
For more details about the core structure and instruction set, see CR16B Programmer’s Reference Manual, Revision 2.2,
September 1999 (Literature Number: 633150-001)
1.3.2
The BIU enables access to off-chip memory and I/O devices. It is organized in zones, as follows:
Configuration registers that control the bus transactions are associated with each zone and are part of the BIU module, See
Section 4.1 on page 67 for details. For details about the link between DEV environment and the BIU, see Section 1.4.3 on
page 29.
1.3.3
RAM. The 4096-byte on-chip RAM is mostly used for the storage of program variables and the stack. It can also store short
programs used while the flash memory is being updated. Part of the on-chip RAM is reserved for use by the core develop-
ment tools monitor program, TMON (part of the Booter). For information, see the CompactRISC
sion 3.1.2.3 Release Letter, March 2001.
ROM. The PC87591L-N05 is equipped with a small pre-programed ROM, which functions as a boot ROM.
External Flash. The PC87591L-N05 hardware arbitrates flash usage by the core firmware and the host processor BIOS pro-
gram when Shared-BIOS configuration is selected. Flash sharing is based on in-parallel “cycle stealing” so both the host
processor and the core can execute code in parallel from the same memory device. The host processor typically copies the
flash contents to the host’s main memory (DRAM) on system boot to improve access time to it and enable execution when
the flash’s contents is compressed. It is important to do this early in the boot process to reduce resource contention between
the core and the host.
1.3.4
The ICU (Interrupt Control Unit) collects interrupts from various internal and external (through the MIWU) sources and uses
the vectored interrupt mechanism to notify the core of events. It supports 31 maskable interrupt inputs (see Table 15 on
page 97 for the interrupt assignment) and, via the PFAIL input, a Non-Maskable Interrupt (NMI).
The MIWU (Multi-Input Wake-Up) module enables collecting various internal and external interrupt sources (events), gen-
erates interrupts in Active mode and enables the PC87591L-N05 to return from Idle mode to Active mode. The core can
separately enable or disable each wake-up conditions. The PC87591L-N05 has a total of 28 wake-up signals, some of which
are grouped together to generate a single interrupt signal to the ICU.
The PMC (Power Management Controller) controls PC87591L-N05 power consumption according to the required activity level.
Power consumption is adjusted by controlling the clock frequency and selective enabling/disabling of three power modes: Active,
Idle and Power Off. Activity can be resumed by external events (through the MIWU) or internal events, such as a periodic wake-up.
The Clock Generator provides clocks for the various core-related on-chip modules. These clocks are generated directly
from a 32.768 KHz crystal or from the on-chip High-Frequency Clock Generator (HFCG). The HFCG generates the high-
frequency clock using the RTC’s 32.768 KHz clock signal as a reference. The PC87591L-N05 operation frequency is set by
programing the HFCG registers. The PMC enables and disables high-frequency clock generation, according to the required
power mode.
The GPIO Ports (General-Purpose Input/Output) module consists of up to 92 GPIO port signals that serve as an interface
to and provide control for the PC system. Some of these GPIO port signals share their pins with an alternate function (see
Table 6 on page 49), with which they may be mutually exclusive. When configured as inputs, some of these signals can in-
terrupt the core when an event is detected, even if the device is in Idle mode. An example is the SWIN input, which is ded-
icated to the PC On/Off switch.
• Zone 0 and 2 - Expansion memory (flash and/or SRAM). This memory may be used for the core code, data and/or
• Zone 1 - This zone is available for off-chip in DEV environment only and is used for emulating the operation of the
• I/O Zone - This zone can be used for I/O expansion. In DEV environment, it can be used to recreate GPIO signals,
the host BIOS program.
on-chip base memory, using an off-chip SRAM. In IRE and OBD environments, the configuration of this zone should
be the same as in DEV environment to enable cycle-by-cycle compatibility.
whose pins are used for the development system interface.
Processing Unit
Bus Interface Unit and Memory Controller (BIU)
Memory
Peripherals
(Continued)
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PC87591x Tmonlib Ver-
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