pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 106
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pc87591l-n05
Manufacturer Part Number
pc87591l-n05
Description
Lpc Mobile Embedded Controller
Manufacturer
National Semiconductor Corporation
Datasheet
1.PC87591L-N05.pdf
(401 pages)
- Current page: 106 of 401
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4.0 Embedded Controller Modules
The MIWU outputs WKO10 through WKO37 may be connected to the Interrupt Control Unit (ICU) to generate an interrupt
associated with the specific MIWU output. The WKOxx behaves as follows:
Note: To enable and disable ICU interrupts generated by their associated WKOxx output of the MIWU, use the ICU mask
In addition, the MIWU provides four interrupt request lines: WKINTA, WKINTB, WKINTC and WKINTD (see Figure 31 on
page 105). These are routed to the ICU (except WKINTB) and can request an interrupt if a valid trigger condition occurred
on any of the enabled input sources within the group of eight inputs associated with the interrupt line. For a detailed summary
of the interrupts available, see Table 16 on page 103.
4.4.3
For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 32.
MIWU Register Map
• When the respective WKENxx bit is cleared, the WUIxx is connected to the ICU directly (bypassing the edge detec-
• When the respective WKENxx bit is enabled, the output of the pending bit, WKPDxx, is connected to WKOxx.
tors and pending bits). The ICU can be configured to use the signal as a level or edge triggered interrupt.
register in the ICU.
MIWU Registers
WKEDG1
WKEDG2
WKEDG3
WKEDG4
WKPND1
WKPND2
WKPND3
WKPND4
WKEN1
WKEN2
WKEN3
WKEN4
WKPCL1
WKPCL2
WKPCL3
WKPCL4
Mnemonic
Edge Detection Register
Edge Detection Register
Edge Detection Register
Edge Detection Register
Pending Register
Pending Register
Pending Register
Pending Register
Enable Register
Enable Register
Enable Register
Enable Register
Pending Clear Register
Pending Clear Register
Pending Clear Register
Pending Clear Register
(Continued)
Register Name
106
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WO
WO
WO
WO
Revision 1.2
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