pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 233

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
4.0 Embedded Controller Modules
Debug Transmit Lock Register (DBGTXLOC)
DBGTXLOC is a byte-wide read/write register. The PID field of this register is used as a semaphore for locking the Tx chan-
nel for a specific processor. If TINT is not active (1), this register is loaded with F
active (0), it is not affected by a Warm or Internal reset. At Power-Up reset, the register is always loaded with 0F
register format is shown below.
Location: 00 FDE4
Type:
Debug Transmit Status Register (DBGTXST)
DBGTXST is a byte-wide read/write register. This register is written by a processor to indicate the message length, which is
used by the Tx data link to set the length of the serial shift register and by the processor software to define the message
length parameter. While TINT is inactive, this register may be written to at any time. While TINT is active, the contents of
this register are locked and can be read by the host via the TAP controller status word MSG_LEN field. While TINT is inac-
tive, DBGTXST is cleared on reset. While TINT is active, only Power-Up reset clears DBGTXST. The register format is
shown below.
Location: 00 FDE2
Type:
Debug TINT Assert Register (DBGTINT)
This is a byte-wide write-only register used to assert TINT. The register format is shown below.
Location: 00 FDE6
Type:
Bit
Name
Bit
Bit
Name
Bit
Name
Reset
3-0
7-4
Bit
7-1
Bit
0
ASSERT (Assert TINT Control). Writing 1 to this bit asserts the TINT output. TINT is de-asserted during
Update_DR state of SCAN_TX or during Power-Up reset.
Reserved.
PID (Processor Index). Indicates which processor currently has control over the Tx channel. When TINT
becomes active, the value of PID is locked. On the Update_DR state of SCAN_TX instruction, PID is reset to
F
Reserved.
16
R/W
0
F
R/W
WO
16
16
after the host reads the data.
-E
:
16
: Processor ID index. When the PID field holds any of these values, write operations of values other
16
than F
Semaphore free indication. When the PID field holds this value, write operations may capture the Tx
for processor use.
16
16
7
7
0
7
0
16
are ignored.
6
0
6
6
0
Reserved
Reserved
5
0
5
5
0
(Continued)
Reserved
Description
Description
233
4
0
4
0
4
3
1
3
0
3
16
on Warm or Internal reset. If TINT is
2
1
2
0
2
PID
MSG_LEN
1
1
1
0
1
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ASSERT
0
1
16
0
0
0
. The