pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 52

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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2.0 Signal/Pin Description and Configuration
2.4.2
For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 32.
Register Map
Module Configuration Register (MCFG)
The MCFG register is a read/write, byte-wide register. It is used for global system configuration and setup.
Write operations to the MCFG register should write zeros to all reserved bits. On reset, non-reserved bits of MCFG are
cleared to 0. MCFG can be written in Active mode only. Its contents is preserved in Idle mode.
In IRE and OBD environments, all MCFG fields should be used to designate associated pins as GPIO ports or their alternate
functions. In DEV environment, the pins are always allocated for development system use. The I/O ports functionality can
be implemented using off-chip logic.
To guarantee binary and cycle-by-cycle compatibility among the different environments, define the MCFG fields as required
for IRE and OBD even when in DEV environment, and use the I/O Expansion protocol to build an off-chip implementation
of the I/O ports when they are used by the application.
ADBs or ISE systems use the MCFG Shadow (MCFGSH, write only) register to select the functionality of the signal that
reaches the user’s application.
All write operations to the MCFG must be immediately followed by a write to the MCFG Shadow (MCFGSH) register. This
register is part of the development system and is accessed by an access to the I/O zone (SELIO).
MCFG is loaded with either 40
Software should load MCFGSH with the MCFG register’s value after reset.
The format of MCFG (and MCFGSH) is as follows:
MCFG Location:
MCFGSH Location: 00 FBFE
Type:
Bit
Name
Reset
Bit
0
1
System Configuration Registers
ENEIO (Enable Expansion I/O). This bit enables the use of the I/O Expansion protocol for expanding the
amount of GPIO pins available to the application. In IRE and OBD environments, when ENEIO is cleared, the
associated pins are used as GPIO signals. When set, enables the use of BIU I/O zone (SELIO) for the interface
with off-chip logic. Use the BIU I/O zone configuration to select the access parameters to the I/O Expansion
logic and its bus width.
ENEMEM (Enable Expansion Memory). This bit enables the use of the expansion memory for expanding the
amount of memory available to the application to more than what is provided on chip. When cleared, the
associated pins are used as GPIO signals. When set, enables the use of BIU zone 0 (SEL0) and the associated
address and data lines for the interface with flash or SRAM devices. Use BIU zone 0 configuration to select the
access parameters to the expansion memory and its width.
GTMON
See text
7
00 FF10
MCFG is R/W; MCFGSH is WO
MCFG
EICFG
IOEE1 and
IOEE2
PTWRL
PTWRH
PNMR
Mnemonic
HOSTWAIT ENZONE2
16
16
16
or C0
6
1
Module Configuration Register
External Interrupts Configuration Register
Input to Output Echo Enable Register 1 and 2
Protection Word Low Register
Protection Word High Register
Pin Multiplexing Register
16
on reset. See the description of GTMON for behavior of bit 7 during reset.
5
0
Register Name
Description
52
4
0
CLKOM
(Continued)
3
0
EXMEM16
R/W or RO
R/W or RO
2
0
Type
R/W
R/W
R/W
R/W
ENEMEM
1
0
ENEIO
0
0
Revision 1.2