pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 48

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

www.national.com
2.0 Signal/Pin Description and Configuration
2.3
During V
resistors set these signals to 0. These resistors are active only during V
nected to V
Setting the Environment
ENV0 and ENV1 determine the operating environment. Table 4 shows the settings allowed. Pulling both ENV0 and ENV1
to 1 produces unpredictable results. In IRE and OBD environments, the TRIS strap input may be used for floating all the
device signals. In other cases it should be kept low.
Figures 1 on page 24, 4 on page 30 and 5 on page 31 demonstrate how to configure the PC87591L-N05 for IRE, OBD and
DEV environments, respectively, using the ENV0-1 signals.
Other Strap Pin Settings
Table 5 provides brief descriptions of other strap inputs. For details on SHBM and TRIS, see Section 5.3 on page 262 and
Section 4.20.4 on page 236, respectively.
System Load on Strap Pins
The loads on the strap pins should not cause the voltage on them to drop below V
rise above V
If the load caused by the system on the strap pins exceeds 10 A, use either an external pull-down resistor to keep the pin
at 0 or a pull-up resistor with lower resistance to keep the pin at 1.
To reduce power consumption, in Idle mode, pins with strap inputs on them and a signal function other than GPIO are put
in TRI-STATE or drive the strap-pin value. For pins with strap inputs that function as GPIO, it is recommended that the ap-
plication drive the strap value as output to the value defined by the strap pin. For pins with strap and address line function-
ality, when the address configuration is enabled, the signal is driven by the hardware to its strap value on reset.
Strap Pin Status Register (STRPST)
The STRPST register is a byte-wide, read-only register. It enables the software to read the value set to strap pins during
Power-Up reset. STRPST bits provide the value of their respective strap input. See Table 5 for bit details.
Location: 00 FF12
Type:
Reset Value: According to external straps
BADDR1-0 SuperI/O Configuration Base Address; see Table 37 on page 297
SHBM
TRIS
Bit
Name
Reset
Strap Pin
STRAP PINS
CC
RO
CC
Power-Up reset, the ENV(0-1), TRIS, SHBM and BADDR strap input signals are sampled. Internal pull-down
IL
Disables shared memory with host BIOS Enables shared memory with host BIOS
Normal operation
may be used to set them to 1.
when they should be low (0). See Section 7.3.2 on page 339.
16
7
Internal Pull-Down (0)
IRE
OBD
DEV
1. When set to 1, the PC87591L-N05 is put in TRI-STATE
Environment
6
mode.
Table 4. Environment Pin Settings
Reserved
Table 5. Other Strap Pin Settings
5
While in IRE and OBD environments, causes PC87591L-N05 to
float its output and I/O signals for system test purposes and clip-on
ISE use
ENV0
0
0
1
48
4
(Continued)
ENV1
CC
0
1
0
Power-Up reset. An external 10 K resistor con-
3
External Pull-Up (1)
IH
BADDR1
when the pins should be high (1), or to
TRIS
0
0
0
2
1
1
BADDR0
1
SHBM
0
Revision 1.2