pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 281

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
5.0 Host Controller Interface Module
When an input event is detected, the corresponding status bit in both host and core status registers is set to 1, regardless
of any Routing Enable bit setting. If both the status bit and a Routing Enable bit corresponding to a specific event are set to
1 (no matter in what order), the output pin corresponding to that Routing Enable bit is asserted.
A status bit is cleared by writing 1 to it. Writing 0 to a status bit does not change its value. Clearing the routing enable bit of
an event prevents it from issuing the corresponding system notification (output event) but does not affect the status bit.
Figure 97 shows the routing scheme of detected wake-up events to the various means of system notification (i.e., output
events).
Both the core and the host have status registers; thus both core and host software can monitor the various event status bits.
This enables handling of events via wake-up logic that is implemented as part of the Embedded Controller firmware, and
passing the wake-up notifications through the Power Management host-interface protocol. The core uses a mask register
(WK_SMIENn) to define which of the status bits it should respond to.
It is recommended that each of the wake-up sources be handled by one handler routine on the host (i.e., SMI, SCI or IRQ
triggered) or the core.
Software Event
A software event may be used to trigger an interrupt to the host and/or core via software control, as shown in Figure 96.
A software event to the host is active when Software Event Status bit in WK_STS0 register is set. When that status bit is
set, WK_EN0 bit 6 enables the generation of an interrupt to the host.
A software event to the core is active when the Software Event Status bit in MSHES0 register is set. When that status bit is
set, Bit 6 in MSHEIE0 register enables generation of an interrupt to the core.
The software events are activated (i.e., the status bits in WK_STS0 and MSHES0 registers are set) by writing 1 to the Soft-
ware Event Status bit in WK_STS0 register when that bit is cleared (the Software Event Status bit in MSHESO is set by a
change of the respective bit in WK_STS0, from 0 to 1). The host can activate the software event when V
core can activate the software event by accessing the MSWC host registers through the Core Access to Host-Controlled
Modules bridge (even when V
The software event clearing scheme is defined by HSECM bit in MSWCTL1 register, as follows:
When HSECM bit is cleared, the host Software Event Status bit in WK_STS0 register is cleared by writing 1 to it when it is
set (i.e., writing 1 to Host Software Status bit in WK_STS0 register functions as a toggle operation). The core Software Event
Status bit in MSHES0 is cleared by writing 1 to it (write 1 to clear). This mode is useful when the software event interrupts
the host and is handled by it (Figure 96A).
B. HSECM bit (MSWCTL1 Register) = ‘1’
A. HSECM bit (MSWCTL1 Register) = ‘0’
WK_STS0
WK_STS0
To MSWC IRQ
To MSWC IRQ
(Host Event)
(BIT 6)
(Host Event)
(BIT 6)
{
{
Read Status
Read Status
Write ‘1’ to
Write ‘1’ to
the bit
the bit
DD
is off).
Figure 96. MSWC Software Event Generation Scheme
WK_EN0
WK_EN0
(Bit 6)
(Bit 6)
Toggle
Set
Set
Domain Domain
WK_STS0
WK_STS0
(BIT 6)
(BIT 6)
(Continued)
Host
Set
281
Core
MSHES0
MSHES0
(BIT 6)
(BIT 6)
MSHEIE0
MSHEIE0
Clear
Clear
(Bit 6)
(Bit 6)
Clear
Read Status
Read Status
Write ‘1’ to
Write ‘1’ to
the bit
the bit
(Core Event)
(Core Event)
To MIWU
To MIWU
DD
}
}
is present. The
MSHES0
MSHES0
(BIT 6)
(BIT 6)
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