pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 33

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
1.0 Introduction
Accessing Base Memory
The base memory is used for storing code and data required for basic boot operations. The rest of the code and data are
stored in the expansion memory shared by the core firmware and host BIOS.
IRE and OBD Environments (On-Chip Base Memory). In IRE and OBD environments, the on-chip ROM is used as base
memory. The access time to it is controlled by BIU zone 1. To allow cycle-by-cycle compatibility with DEV environment, this
zone should be programed in the same way for all environments. Thus to maximize on-chip ROM performance, configure
BIU zone 1, as described in Section 4.1.11 on page 84.
DEV Environment (Off-Chip Base Memory). In DEV environment (when on-chip ROM is disabled), the boot code and
constant data are stored in off-chip base memory. The size of the off-chip base memory is 4 Kbytes.
Accessing Expansion Memory
The expansion memory of the PC87591L-N05 is divided into two zones when BIU zone 2 is enabled:
When BIU zone 2 is disabled, the whole expansion memory of the PC87591L-N05 is controlled by the BIU zone 0 configu-
ration registers.
Access to expansion memory is enabled only after:
The interface signals to the expansion memory are:
Figure 6 on page 33 shows how on-chip and off-chip base memory are mapped to the PC87591L-N05 address space.
• Low Zone - for addresses with base memory in the range of 00 1000 to 03 FFFF. The access time to this zone is
• High Zone - for addresses with base memory in the range of 01 0000 to 1F FFFF. The access time to this zone is
• The pins used for the memory interface are configured to operate as expansion memory interface signals (see
• The BIU zone 0 register and/or zone 2 configuration registers (SZCFG0, SZCFG2), which control the memory access
• Zone 0 or zone 2 is selected for 00 1000
• 8-bit flash or SRAM: SEL0, SEL2, RD, WR0, D0-7 and A0-20 (fewer address lines may be used with a smaller flash).
• 16-bit flash or SRAM: SEL0, SEL2, RD, WR0-1, D0-15 and A1-20 (fewer address lines may be used with a smaller
ROM Size
controlled by the BIU zone 2 configuration registers. The zone 2 memory can be configured for 64K, 128K, 192K or
256K ranges. The configuration of the zone 2 range is selected by bits 8-9 of Protection Word Low Register (PTWRL)
(see Page 54).
controlled by the BIU zone 0 configuration registers.
Section 2.4 on page 49 for details on the alternate functions configuration).
parameters (e.g., bus width and access time), is set to support the configuration in use.
figuration Register (MCFG) (see Page 52).
flash).
64 K
2 M
4 K
Core Address Map
0
(Continued)
Figure 6. Base Memory Address Mapping
16
On-Chip Base Memory
00 DFFF
16
33
Expansion memory address range by bit 5 of Module Con-
4 K
Off-Chip Base Memory
00 0FFF
00 0000
Access Time
Zone 1
Control
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