pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 78

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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4.0 Embedded Controller Modules
4.1.7
When FRE bit in SZCFGn register is 1, the fast read bus cycle is enabled for zone n. The fast read bus cycle takes one clock
cycle.
At the start of the T1-2 clock cycle, the address is placed on the address bus, and SELn and RD are activated. WR0-1 are
inactive, indicating a read bus cycle. At the end of the clock cycle, the BIU samples the data. SELn and RD are deactivated
in the following clock cycle, unless another read from the same zone follows. If a write to the same zone follows and late
write is configured, SELn remains activated. The address remains valid until the start of the clock cycle after the T1-2 clock
cycle.
The fast read bus cycle cannot be extended by adding wait cycles (WAIT field in SZCFGn register is ignored during this bus
cycle). Additionally, hold cycles cannot be added (HOLD field in SZCFGn register is also ignored). When a write bus cycle
immediately precedes, in sequence, a fast read bus cycle, an idle clock cycle is forced between the two; see Figure 22.
Note that when the core attempts to access more bytes than the configured bus width (i.e., a word), the transaction is broken
up into “basic” (T1-2) bus cycles.
4.1.8
The I/O expansion bus cycles support the implementation of on-chip I/O port functionality (when the pins of the on-chip I/O
ports are used to support DEV environment) and/or additional ports, using off-chip external logic.
I/O expansion bus cycles access the off-chip I/O device using the following signals:
The design minimizes the off-chip logic required to implement the I/O ports. It is costly to implement a port with pins individ-
ually configured for input or output. Implementing ports for input only or output only reduces expenses.
I/O expansion bus cycle is not generated during an access to a port register if one of the following conditions occurs:
• SELIO.
• Address lines A0-7.
• The RD and WR0-1 signals may be used.
• A port pin is available on-chip.
• All port pins are inputs and the port is being written.
Fast Read Bus Cycle
I/O Expansion Bus Cycles
Bus State
A0-20
CLK
SELx
SELy
D0-15
RD
WR0-1
BST0-2
(x
(y
y)
x)
T
Idle
Read
Fast
Figure 22. Fast Read Bus Cycle
T1-2
In
(Continued)
T1
Late Write
78
T2
Out
Cycle
Idle
T
Idle
Read
Fast
T1-2
In
T1
Revision 1.2