pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 279
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pc87591l-n05
Manufacturer Part Number
pc87591l-n05
Description
Lpc Mobile Embedded Controller
Manufacturer
National Semiconductor Corporation
Datasheet
1.PC87591L-N05.pdf
(401 pages)
- Current page: 279 of 401
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Revision 1.2
5.0 Host Controller Interface Modules
SIB Control Register (SIBCTRL)
This register allows the core to control the SIB controller operation.
Location: 00 FCEA
Type:
Bit
Name
Reset
7-4
Bit
0
1
2
3
R/W1S CSRD (Core Read from SIB). Writing 1 to this bit starts a read from the SIB; the read is based on the
R/W1S RTCMR (Real-Time Clock (RTC) Master Reset). Writing 1 to this bit generates a reset pulse to the
Varies per bit
Type
R/W
RO
CSAE (Core to SIB Access Enabled).
0: Core access to the SIB bus is disabled (default)
1: Core access to the SIB bus is enabled. The logical device is selected by the CRSMAE register.
address and enabled device specified in CRSMAE register. A write of 0 to this bit is ignored. This bit
is cleared when the read operation is completed, indicating that the data is ready in IHD register.
CSWR (Core Write to SIB). The bit is set by a write operation to IHD register. It is cleared when the
write to the SIB is completed.
RTC module. This bit is cleared by the hardware once the reset pulse is completed. Writing 0 to this
bit is ignored.
Reserved.
16
7
0
6
0
Reserved
5
0
(Continued)
279
4
0
Description
RTCMR
3
0
CSWR
2
0
CSRD
1
0
www.national.com
CSAE
0
0
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