pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 102

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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4.0 Embedded Controller Modules
Edge Interrupt Clear Register 0 (IECLR0)
The IECLR register is used to clear pending, edge-triggered interrupts.
Location: 00 FE12
Type:
Edge Interrupt Clear Register 1 (IECLR1)
The IECLR register is used to clear pending, edge-triggered interrupts.
Location: 00 FE14
Type:
4.3.5
Initializing
The recommended initialization sequence is:
1. Initialize both the INTBASE register and the interrupt stack pointer of the core.
2. Prepare the interrupt routines of the interrupts used.
3. Clear edge interrupt used.
4. Set relevant bits of the peripherals.
5. Set relevant bits in IENAM register.
6. Set PFAIL register.
7. Enable core interrupt.
Clearing
Clearing an interrupt request before it is serviced may cause a spurious interrupt (i.e., when the core detects an interrupt not
reflected by IVCT). Clear interrupt requests only when interrupts are disabled. Clear IENAM bits and ISTAT bits while the
core interrupts are disabled (i.e., bits I and/or E in PSR register are cleared).
Nesting
The IENAM registers can be used in interrupt handlers to allow interrupt nesting. When the core acknowledges an interrupt, it
disables maskable interrupts by clearing bit I in PSR register and executes the interrupt service routine. This routine can enable
nested interrupts by setting bit I in PSR register and can use the IENAM registers to control which interrupts are allowed.
Bit
Name
Bit
Name
15-1 IEC15-1 (Edge Interrupt Clear). Each bit clears the corresponding bit in ISTAT0 register. Writing to the bit
15-0 IEC31-16 (Edge Interrupt Clear). Each bit clears the corresponding bit in ISTAT1 register. Writing to the bit
Bit
Bit
0
Usage Hints
Reserved.
positions of level-triggered interrupts has no effect. Read always returns FFFF
INT15 to INT1, respectively. Each bit is encoded as follows:
0: No effect
1: Pending edge-triggered interrupt cleared
positions of level-triggered interrupts has no effect. Read always returns FFFF
INT31 to INT16, respectively. Each bit is encoded as follows:
0: No effect
1: Pending edge-triggered interrupt cleared
WO
WO
15
15
16
16
14
14
13
13
12
12
11
11
10
10
(Continued)
9
9
IEC15-1
Description
Description
102
IEC31-16
8
8
7
7
6
6
5
5
16
16
. IEC31 to IEC16 correspond to
4
4
. IEC15 to IEC1 correspond to
3
3
2
2
1
1
Revision 1.2
Res.
0
0