pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 305

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

6.0 Host-Controlled Modules and Host Interface
(Continued)
FWH Write Cycle:
1. START: 1110
(0xE).
16
2. ID field: FWH ID nibble (compared with bits 7-4 of shared memory; see “Shared Memory Configuration Register” on
page 312).
3. Address: Eight address nibbles MS nibble first (see usage below).
4. DATA: Two data nibbles, LS nibble first (D3-D0, D7-D4).
5. TAR (two cycles).
6. SYNC.
7. TAR (two cycles).
The ID field is compared with bits 7-4 of shared memory; see “Shared Memory Configuration Register” on page 312. If the
two match, the PC87591L-N05 continues handling the transaction; if they do not match, the current LPC-FWH transaction
is ignored.
LPC-FWH Address translation: The address field in the LPC-FWH transaction is constructed of eight nibbles. The first seven
correspond to the first LS seven address nibbles (A27-A0) as follows: The first nibble that appears corresponds to addresses
A27-A24, the second to A23-A20, until the seventh incoming nibble, which corresponds to addresses A3-A0. Incoming nib-
ble number eight is ignored. The MS bits of the 32-bit addresses are ‘1111’ (A31 - A28).
Core Interrupt
Whenever there is an LPC or FWH transaction that is responded to by any of the PC87591L-N05 logical devices, a positive
pulse is generated on the Host Access Wake-Up input of the MIWU module. This interrupt may be used to wake up the core
for handling any host activity.
CLKRUN Functionality
The PC87591L-N05 supports the CLKRUN I/O signal, the use of which is highly recommended in portable systems. This
signal is implemented according to the specification in PCI Mobile Design Guide, Revision 1.1, December 18, 1998. The
PC87591L-N05 supports operation with both a slow and stopped clock in ACPI state S0 (the system is active but is not being
accessed). The PC87591L-N05 drives the CLKRUN low to force the LPC bus clock into full speed operation when an IRQ
is pending internally and waiting to be sent through the serial IRQ.
LPCPD Functionality
The PC87591L-N05 supports the LPCPD input. This signal is used when the V
chip supply is not shared by all residents
DD
of the LPC bus. The LPCPD signal conforms with Intel’s LPC Interface Specification, Revision 1.0. Note that if the
PC87591L-N05 power supply exists while LPCPD is active, it is not mandatory to reset the PC87591L-N05 when LPCPD is
de-asserted.
Revision 1.2
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