pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 193

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
4.0 Embedded Controller Modules
ACB Control Register 1 (ACBnCTL1)
The ACBnCTL1 register is a byte-wide, read/write register that configures and controls the ACB module. On reset, the
ACBnCTL1 is cleared (00
Location: Channel 1 - 00 FF66
Type:
Channel 1 and Channel 2
Channel 3 and Channel 4
Bit
Name
Reset
Bit
Name
Reset
Bit
0
1
2
3
4
START. Should be set when a Start Condition must be generated on the ACCESS.bus.
– If the PC87591L-N05 is not the active bus master (MASTER in ACBnST register is set to 0), setting START
– If the PC87591L-N05 is the active master of the bus (MASTER in ACBnST register is set to 1), when START is
The START bit is cleared either when the Start Condition is sent or on detection of a Bus Error (BER in ACBnST
register is set to 1).
This bit should be set only when in Master mode or when requesting Master mode.
STOP. In Master mode, setting this bit generates a Stop Condition, which completes or aborts the current
message transfer. This bit clears itself after STOP is issued.
INTEN (Interrupt Enable). When INTEN is cleared (0), the ACB interrupt is disabled. When INTEN is set,
interrupts are enabled. An interrupt is generated (the interrupt signals to the ICU are high) on one of the
following events:
– An address match is detected (NMATCH in ACBnST register is set to1 and NMINTE in ACBnCTL1 register is
– A Bus Error occurs (BER in ACBnST register is set to 1).
– A negative acknowledge is received after sending a byte (NEGACK in ACBnST register is set to 1).
– If DMA is not enabled, acknowledgment of each transaction (same as the hardware set of SDAST in ACBnST).
– In Master mode, if STASTRE in ACBnCTL1 register is set to 1 after a successful start (STASTR in ACBnST
– Detection of a Stop Condition while in Slave mode (SLVSTP in ACBnST register is set to 1).
DMAEN (DMA Enable - for Channel 3 and Channel 4). When this bit is set, the DMA interface is enabled. A DMA
request is generated at the end of any data transaction (set of SDAST in ACBnST). If INTEN is set, interrupts are
generated on the occurrence of any error or a new match).
ACK (Acknowledge). When acting as a receiver, this bit holds the value of the next acknowledge cycle. It
should be set when a negative acknowledge must be issued on the next byte. This bit is cleared (0) after the
first acknowledge cycle.
This bit is ignored when in Transmit mode. It cannot be reset by software.
Channel 2 - 00 FFE6
Channel 3 - 00 FC46
Channel 4 - 00 FC66
R/W
generates a Start Condition as soon as the ACCESS.bus is free (BB in ACBnCST register is set to 0). An ad-
dress transmission sequence should then be performed.
set, a write to ACBnSDA register generates a Start Condition. ACBnSDA data is then transmitted as the slave’s
address and the requested transfer direction.
In case of a Repeated Start Condition, the set bit may be used to switch the direction of the data flow between
the master and the slave or to choose another slave device without using a Stop Condition in between.
set to 1).
register is set to 1).
STASTRE
STASTRE
7
0
7
0
16
).
NMINTE
NMINTE
16
16
16
16
6
0
6
0
GCMEN
GCMEN
5
0
5
0
(Continued)
ACK
ACK
Description
193
4
0
4
0
Reserved
DMAEN
3
0
3
0
INTEN
INTEN
2
0
2
0
STOP
STOP
1
0
1
0
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START
START
0
0
0
0