pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 29

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
1.0 Introduction
See Figure 1 on page 24 for a system example in IRE environment. In this environment, the ENV0, ENV1 and TRIS strap
pins do not need any external pull-up resistors.
1.4.2
OBD environment is used for debugging the PC87591L-N05 firmware while it is mounted on its final production board. All
pins have their IRE functionality, and the interface to a debugger running on the host is enabled using the JTAG based de-
bugger interface. In OBD Environment, code is executed from the expansion memory. Breakpoints on data and code access
may be applied using the core hardware breakpoint mechanism. The monitor stored in the on-chip ROM is used as part of
the debugging environment.
OBD environment is binary and cycle-by-cycle compatible with IRE environment.
See Figure 4 on page 30 for a system example in OBD environment. In this environment, the ENV0 and TRIS strap pins
are left unconnected, and ENV1 requires an external pull-up resistor.
1.4.3
DEV environment is used in Application Development Boards (ADBs) or In System Emulators (ISEs). In this mode, the on-
chip ROM and the external flash are replaced with off-chip SRAM memory to allow flexible and fast development of appli-
cation code. Some pins are allocated for development system use, and the GPIO functions associated with the pins are rep-
licated using off-chip logic as part of the ADB system. DEV environment is binary and cycle-by-cycle compatible with OBD
and IRE environments.
In this environment, the pins of ports PH, PI, PJ, PK, PL and PM are allocated for the interface to the off-chip base memory,
core status signals, reset output and a breakpoint input. The system may regain these ports using the I/O Expansion protocol
and off-chip logic, while maintaining cycle-by-cycle and binary compatibility with IRE and OBD environments. Using the
same software, this environment is binary and cycle-by-cycle compatible with IRE and OBD environments. All features of
IRE environment can be implemented either directly or by using additional external logic.
See Figure 5 on page 31 for a system example in DEV environment. In this environment, the ENV0 strap pin needs an ex-
ternal pull-up resistor and the ENV1 and TRIS pins are left unconnected.
1.5
The PC87591L-N05 has two address domains: core and host. The host address space is composed of the host I/O address
space and the host memory space. Section 1.5.1 discusses the mapping of memories and peripherals into the core address
space. Figure 3 shows the memory map and the shared access schemes that are possible. Section 1.5.2 discusses the
mapping of the host address space and ways of accessing it.
The PC87591L-N05 enables several memories in the core address space to have restricted access to the host. These mem-
ories are referred to as “shared memory” or “shared BIOS”. In addition, the core can access the Host Controlled Functions.
Section 1.5.2 and Section 1.5.3 discuss these instances of cross-domain access, respectively.
1.5.1
The memory and I/O devices are directly mapped into the 2 Mbyte address space of the core. The core address space can
include both code and data. However, access to data stored in the first 64 Kbytes of the address space is more efficient.
Host Address Domain
4G
0
MEMORY MAP
Space
OBD Environment
DEV Environment
Core Address Domain Memory Map
Mem
64K
0
Space
(Continued)
I/O
Core Access to Host
Controlled Functions
Host Domain Memory
Figure 3. Memory Domains
29
(End of Core Memory
Core Address Domain
2M
4K
0
Wrap-Around 2M)
Expansion
Internal ROM
External
Memory
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