pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 63

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
3.0 Power, Reset and Clocks
3.2.4
Warm reset is activated on the falling edge of RESET1 input. If Warm reset and V
V
During a Warm reset, the PC87591L-N05 responds as follows:
During Warm reset, strap pins are not sampled and the configuration determined at V
quent Warm resets.
The PC87591L-N05 core domain and some parts of the host-core interface functions can operate when RESET1 is still as-
serted (low). Some parts of the Host Domain Functions that are reset by the Host Domain reset (see following section) are
kept reset as long as RESET1 is asserted.
3.2.5
Using RESET2 Input
The RESET2 input signal is enabled as an alternate function on one of two pins. The RST2EN field of the ”Protection Word
High Register (PTWRH)” (see Page 55) is used to define whether the RESET2 input is enabled and, if so, on which of the
two pins.
Note that enabling RESET2 input on either of the signals causes that pin to be used as an input GPIO with an interrupt input
associated with it. It is recommended to use this interrupt function to interrupt the core when a RESET2 event occurs and
to use the interrupt routing to stop activities and resume default values to some system elements not directly reset by the
event.
Host Domain Reset Actions
The reset actions on the host domain are broken into two categories that depend on the reset event source; some of the
actions may happen for both these reset source types and thus are named Host Domain Reset.
Host Domain Hardware Reset: While RESET1 is active, or RESET2 is active and V
Host Domain Hardware reset performs the following actions:
Host Domain Software Reset: This reset is triggered by a write of 1 to bit 1 in SIOCF1 register in the SuperI/O Configura-
tion registers.
Host Domain Software reset performs the following actions:
Note that lock bits and memory protect bits are not reset by software reset; instead, they require a hardware reset to unlock
them; this requirement protects these bits from any faulty or malicious software.
For more details, see Section 6.1.3 on page 303.
Host Domain Reset: This term is used when a bit is reset by either a Host Domain Hardware reset or Host Domain Soft-
ware reset.
• Terminates core executed instructions
• Discards results not yet written to memory
• Eliminates any pending core interrupts and traps
• Clears the internal latch for the core domain’s edge-sensitive external interrupt
• Deactivates the external bus control signals WR(0-1), SEL(0-2), SELIO, RD and BST(0-2)
• Puts the address A(0-20) and data D(0-15) buses in TRI-STATE
• Switches to core domain’s Active mode
• Loads default values into registers, with the exception of:
• Resets the Debugger interface, except for TAP controller
• It brings the LPC interface state machine to its inactive state.
• It resets all SuperI/O configuration registers except for those that are battery-backed (see Section 6.1.8 on page 306).
• It resets Shared Memory Host Controlled registers
• It resets all SuperI/O configuration registers except those noted to be protected from software reset (i.e., bits that are
• It resets Mobile System Wake-Up Control (MSWC) bits and RTC bits marked to be reset by software.
CC
— The Mobile System Wake-Up Control (MSWC) and RTC registers retained by V
— Some registers that are specifically noted to be cleared only by other events
locked from write accesses).
power-up takes precedence.
Warm Reset
Host Domain Reset
(Continued)
63
CC
Power-Up reset occur at the same time,
CC
DD
PP
.
power-up is unaffected by subse-
is on or after V
DD
power-up.
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