pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 64

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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3.0 Power, Reset and Clocks
3.3
The PC87591L-N05 has three clock domains, as shown in Table 10.
Core Domain Clock
The core clock is sourced by the HFCG. The following section gives an overview of the clock domain.
On V
ware. See Section 4.18 on page 212.
On Watchdog reset (or Debugger interface reset), the HFCG is reset.
LPC Clock
The LPC interface is driven by the LCLK input. LCLK frequency can be up to 33 MHz. The clock CLKRUN signal may be
used as part of a power management scheme that slows down the clock; see “CLKRUN Functionality” on page 305.
RTC (32 KHz) Clock
The RTC clock is the reference for the generation of all other clocks in the PC87591L-N05. The clock is enabled at V
er-up and is kept active while V
time. The RTC clock is used for time keeping in the RTC; it is also fed into the Power Management Controller (PMC), which
provides the clock to other functions (such as TWD and ACM) that are active at all times (including Idle).
3.4 TESTABILITY SUPPORT
The PC87591L-N05 supports two testing techniques:
3.4.1
The In-Circuit Testing (ICT) technique, also known as “bed-of-nails”, injects logic patterns to the input pins of the devices
mounted on the tested board. It then checks their outputs for the correct logic levels.
The PC87591L-N05 supports this testing technique by floating (TRI-STATE) all the device pins. This avoids back-driving the
PC87591L-N05 pins by the ICT tester when a device normally controlled by PC87591L-N05 is tested (device inputs are driv-
en by the ICT tester).
To enter TRI-STATE mode, the TRIS pin must be pulled up (by a 10 K
after V
output and I/O pins are floated (TRI-STATE). An exception to this are the power supply pins (AV
AGND, GND), the DAC output pins (DA3-0) and the 32KX2 pin, which do not float in TRI-STATE mode.
3.4.2
The PC87591L-N05 device mounted on the board can be tested using the XOR-Tree technique. This test also checks the
correct connection of the device pins to the board.
To enter XOR-Tree mode, BADDR0 and BADDR1 pins must be pulled up (by a 10 K
must be left unconnected after V
completed, the device pins (including BADDR0-1 and TRIS pins) are connected in a XOR-Tree configuration and are isolat-
ed from the internal PC87591L-N05 functions.
• In-Circuit Testing (ICT)
• XOR-Tree Testing
Clock Domain
CC
CC
CLOCK DOMAINS
1. See Section 6.2.3 on page 318 and Section 6.2.4 on page 319.
Power-Up reset, the HFCG is set to generate a 4 MHz clock. The HFCG frequency can be modified by core firm-
ICT
XOR-Tree Testing
Core
power supply is turned on. After the internal reset (see Section 7.6.2 on page 345) is completed, all the device
LPC
RTC
See Section 4.18
Up to 33 MHz
on page 212
Frequency
32 KHz
PP
CC
is active. Keeping the RTC clock active significantly reduces the PC87591L-N05 wake-up
power supply is turned on. After the internal reset (see Section 7.6.2 on page 345) is
Table 10. PC87591L-N05 Clock Domains
(Continued)
Clock input or on-chip oscillator
LPC clock input
Source
HFCG
64
resistor to V
1
Core domain and host-core interface
RTC, HFCG, TWD, PMC, ACM
CC
LPC bus interface
resistor to V
) in IRE and OBD environments,
Usage
CC
, V
CC
CC
, V
) and the TRIS pin
DD
, V
CORF
CC
Revision 1.2
, V
pow-
BAT
,