pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 54

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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2.0 Signal/Pin Description and Configuration
Protection Word Low Register (PTWRL)
This register can be updated only when HOSTWAIT bit in MCFG register is 1. After HOSTWAIT bit is cleared, PTWRL reg-
ister becomes read only.
PTWRL Location:00 FF06
Type:
Bit
Name
Reset
3-0
7-2
Bit
Bit
4
5
6
7
1
EXWINT46 (Enable EXWINT46).
0: EXWINT46 input is blocked (disabled) while not being read as a GPIO (default)
1: EXWINT46 input is open; this enables the detection of changes on the input to trigger interrupts
Reserved.
Core Boot Block. This field defines the size of the Core Boot Block
The boot block starts at address 00 0000 and ends at the address specified by this field.
Bits
3 2 1 0
1 1 1 1:
1 1 1 0:
Other:
Host Boot Block. This bit defines the use and the size of a Host Boot Block area. Protection is provided by the
Shared Memory function.
0: A 64 Kbyte Host Boot Block is specified
1: No Host Boot Block is available (default)
RTC Lock Default. This bit defines the reset value of the Lock RTC Host Access (LKRTCHA) bit in the Lock
SuperI/O Host Access register (LKSIOHA). This enables preventing host access to the RTC at any time when
the RTC is used by security applications running on the core.
0: RTC Lock is disabled on reset (LKRTCHA=0)
1: RTC Lock is enabled on reset (LKRTCHA=1) (default)
Force MBTA Zero. This bit controls the setting of the host boot block location. See “Shared Memory Core Top
Address Register (SMCTA)” on page 272.
When expansion memory is used for a shared BIOS implementation perform the following:
0: MBSD field in SMCTA register is reset to the implemented on-chip ROM size
1: MBSD field in SMCTA register is reset to 0000
Reserved.
• Set the Force MBTA Zero bit to 1
• Set the Host Boot Block bit to 1
• Locate the host boot block in the boot block of the flash device, used as expansion memory
Reserved
R/W or RO
7
1
16
Description
When in IRE and OBD environments, the core is kept in reset
4K (default)
Reserved
MBTA Zero
Force
6
1
RTC Lock
Default
5
1
Host Boot
Block
16
Description
Description
54
4
1
(default)
(Continued)
3
1
Core Boot Block
2
1
1
1
0
0
Revision 1.2