pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 164

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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4.0 Embedded Controller Modules
TWD Timer 0 Register (TWDT0)
The TWDT0 register is a read/write register. It defines the T0OUT interrupt rate. On reset, this register is initialized to
FFFF
Location: 00 FEE4
Type:
TWDT0 Control and Status Register (T0CSR)
The T0CSR register is a read/write register. It controls the operation and provides the status of the T0 timer. The non-re-
served bits of T0CSR are cleared (0) on reset.
Location: 00 FEE6
Type:
Bit
Name
Reset
Bit
Name
Reset
15-0 PRESET. Defines the counter preset value. Whenever the counter reaches zero, it starts counting down from
7-4
Bit
Bit
0
1
2
3
16
.
this value. The T0OUT frequency is the T0IN frequency divided by (PRESET+1). The allowed values of the
PRESET field are 0001
RST (Reset). When set (1), forces the timer to restart counting in the next input clock rising edge. The bit is
cleared by the input clock rising edge, indicating that the counter resumed its automatic re-triggerable operation.
Writing 0 to this bit is ignored.
TC (Terminal Count). Indicates that the counter has reached zero (terminal count). This bit is cleared each time
the register is read. It is a read-only bit, and data written to it is ignored.
Reserved.
WDLTD (Watchdog Last Touch Delay). The bit is set when the WDCNT is written. It is cleared after watchdog
is updated. (After watchdog is updated, it is safe to switch to Idle mode.)
Reserved.
R/W
R/W
15
1
16
16
7
0
14
1
13
1
16
6
0
through FFFF
Reserved
12
1
11
1
5
0
16
(Continued)
10
1
.
9
1
Description
Description
164
4
0
PRESET
8
1
7
1
WDLTD
3
0
6
1
Reserved
5
1
2
0
4
1
3
1
TC
1
0
2
1
1
1
RST
0
0
Revision 1.2
0
1