pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 90

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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4.0 Embedded Controller Modules
Auto-Initialize Operation
This mode allows the DMAC to continuously fill the same memory area without software intervention.
Initialization
1. Write the two block addresses and byte count into the ADCAn, ADCBn and BLTCn counters, respectively (the BLTCn
2. Program OT bit in DMACNTLn register for Auto-Initialize mode.
3. Set CHEN bit in DMACNTLn register to 1; the channel activates and responds to DMAC transfer requests.
Continuation
When the BLTCn counter reaches 0:
If TC bit is 1:
If TC bit is 0:
4.2.7
In addition to the DMRQn signals, a DMA transfer request can also be initiated by software. The software DMA transfer re-
quest is used for memory-to-memory block copying (in indirect transfers).
When SWRQ bit in DMACNTLn register is 1, the corresponding DMA channel receives a DMA transfer request. When
SWRQ bit is 0, the software DMA transfer request of the corresponding channel is inactive.
For each channel, use the software DMA transfer request, only when the corresponding DMRQn signal is inactive.
4.2.8
For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 32.
DMAC Register Map
Notes:
• The contents of the ADRAn, ADRBn and BLTRn registers are copied to the ADCAn, ADCBn and BLTCn counters,
• The DMAC channel checks the value of TC bit.
• OVR bit in DMASTATn register is set to 1.
• A level interrupt is generated (if enabled by EOVR bit in DMACNTLn register).
• The operation is repeated.
• TC bit in DMASTATn register is set to 1.
• A level interrupt is generated (if enabled by ETC bit in DMACNTLn register).
• The operation is repeated.
• Register names with the suffix n, where n = 0 to 3, are replicated for each channel.
• Unless stated otherwise, bits 21 to 31 are reserved in each of the following registers. Double-word (32-bit) registers
counter should be written last); also write them to the ADRAn, ADRBn and BLTRn registers, respectively (the BLTRn
counter should be written last).
respectively. The BLTCn counter should be written last.
may be accessed word-by-word (word aligned).
Software DMA Request
DMAC Registers
ADCAn
ADRAn
ADCBn
ADRBn
BLTCn
BLTRn
DMACNTLn
DMASTATn
Mnemonic
Device A Address Counter Register
Device A Address Register
Device B Address Counter Register
Device B Address Register
Block Length Counter Register
Block Length Register
DMA Control Register
Status Register
(Continued)
Register Name
90
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Revision 1.2