pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 260

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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5.0 Host Controller Interface Modules
Host Interface PM n Interrupt Control Register (HIPMnIC)
The HIPMnIC register and its bits affect operation in Enhanced mode only (i.e., when EME bit in HIPMnCTL register is set).
In PC87570 Legacy mode, the bits in this registers are ignored. HIPMnIC controls the PM n interrupt signals mode of oper-
ation. HIPMnCTL is 41
Location: Channel 1 - 00 FEBA
Type:
Bit
Name
Reset
5-3
Bit
0
1
2
6
7
IRQB (Host Interrupt Request Control Bit). When the IRQ signal is configured for direct control by the
firmware (HIRQE in HIPMnIE register is 0), IRQB bit is output to the PMnIRQ signal. When read, IRQB bit
returns the current value of the PMnIRQ signal. IRQn signal’s value can be read regardless of the state of
HIRQE in HIPMnIE register.
SMIB (Host SMI Request Control Bit). When the SMI signal is configured for direct control by the firmware
(HSMIE in HIPMnIE register is 0), SMIB bit is output to the PMnSMI signal (if SMIPOL=0, SMIB is output; if
SMIPOL=1, SMIB is inverted before output). When read, SMIB bit returns the current value of the SMI pin. The
SMI signal’s value can be read regardless of the state of HSMIE in HIPMnIE register.
SCIB (Host SCI Request Control Bit). When the SCI signal is configured for direct control by the firmware
(HSCIE in HIPMnIE register is 0), SMIB bit is output to the PMnSCI signal (if SCIPOL=0, SCIB is output; if
SCIPOL=1, SCIB is inverted before output). When read, SCIB bit returns the current value of the SCI pin. The
ECSCI signal value can be read regardless of the state of HSCIE bit in HIPMnIE register.
PLMM (Pulse Level Mode SMI). Sets the hardware-controlled SMI signal mode to Level or Pulse and sets the
pulse width.
When PLMM = 000
low, and a high level is set to issue an interrupt (i.e., the respective OBF is set).
When PLMM
and it toggles high to issue an interrupt (i.e., when the respective output buffer register is written).
The pulse widths are:
Bits
5 4
0 0
0 0
0 1
0 1
1 0
1 0
Other:
SMIPOL (SMI Negative Polarity).
0: SMI output inactive value is low and its active (asserted) value is high
1: Inverted polarity is used. When SMIPOL is set, the SMI signal is either the inverse of what is stored in SMIB or
This bit affects the SMI signal polarity in both PC87570 Legacy and Enhanced modes
SCIIS (SIC on IBF Start). A write of 1 to this bit starts an SCI interrupt on IBF cleared. A write of 0 to SCIIS is
ignored. When read, this bit always return 0.
Channel 2 - 00 FECC
R/W
the output of the SMI pulse shaper (default)
3
0:
1:
0:
1:
0:
1:
SCIIS
Reserved
7
0
Pulse Width
Level interrupt (default)
1-Cycle Pulse
2-Cycle Pulse
4-Cycle Pulse
8-Cycle Pulse
16-Cycle Pulse
16
0, the host interrupts are in Pulse mode. In this mode, the SMI pulse shaper output value is low,
on reset.
2
, the SCI signal functions in Level mode. In this mode, the SMI pulse shaper output value is
SMIPOL
16
16
6
1
5
0
(Continued)
PLMM
Description
260
4
0
3
0
SCIB
2
0
SMIB
1
0
IRQB
0
1
Revision 1.2