pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 224

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

www.national.com
4.0 Embedded Controller Modules
Clock Synchronization
Some operations are related to TCK, others to the PC87591L-N05 main clock and yet others are asynchronous. The
PC87591L-N05 logic guarantees correct operation and a meta-stable protected interface in all its operating modes (i.e., Ac-
tive and Idle).
The core may access the Debugger interface registers only in Active mode.
4.19.4 Test Access Port (TAP)
This section defines the top-level design of the TAP, as shown in Figure 77. Subsequent sections provide detailed TAP de-
sign requirements.
The TAP includes the following elements:
The Instruction and data registers have separate shift register-based paths connected in parallel. These registers have a
common serial data input and a common serial data output connected to the TAP TDI and TDO signals, respectively.
The TAP controller selects between TDI and TDO as the alternative instruction and data register paths.
Further Information
The TAP is based on the test logic in the IEEE 1149.1b-1994 specification. However, since its purpose is to facilitate com-
munication, it does not support IEEE 1149.1b-1194 testing facilities. It is used here to benefit from off-the-shelf bus controller
cards and software and potential future enhancements to the test scheme.
This document includes the relevant rules of this specification. See the following documents for further information.
• TAP signals
• TAP controller
• Instruction Register (IR)
• Data registers.
• For further details and examples of the standard, see IEEE Standard Test Access Port and Boundary-Scan Architec-
• For further details of test bus chips and equipment, see the relevant manufacturer datasheets and application notes,
• For technical background, refer to text books on the subject, for example, Colin M. Maunder and Rodham E. Tulloss,
ture, May 21, 1990
e.g., SCANTM Data book, National Semiconductor 400102.
“The Test Access Port and Boundary-Scan Architecture”, IEEE Computer Society Press Tutorial
TDI
TMS
TCK
.
BYPASS Register
DBGMASKS Register
Instruction Decode
DBGDATA Register
Instruction Register
Figure 77. TAP Block Diagram
(Continued)
Clocks and/or Controls
224
TAP Controller
G
Output Buffer
.
TDO
Revision 1.2