pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 132

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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4.0 Embedded Controller Modules
Counter Clock Source Select
The clock source unit contains two clock source selectors that allow the clock source to be selected independently for each
of the two 16-bit counters from one of the following sources:
4.7.3
The timer/counter and action unit consists of two 16-bit counters, TnCNT1 and TnCNT2, in addition to two 16-bit reload/cap-
ture registers, TnCRA and TnCRB. The timers are down counters capable of triggering events on underflow detection (count
roll-over from 0000
four operation modes described below.
Different interrupts can be triggered on certain conditions, and the functionality of the I/O pins changes depending on the
mode of operation. Therefore the interrupt control and the I/O control are an integral part of the timer/counter unit.
Operation Modes
The MFT16 can be configured to operate in any one of four modes, as summarized in Table 17 and described in this section.
Mode 1, PWM and Counter
PWM can be used to generate precise pulses of known width and duty cycle on the TAn pin. The timer is clocked by the
selected clock. An underflow causes the timer register to be reloaded alternately from the TnCRA and TnCRB registers and
optionally causes TAn output to toggle. Thus, the values stored in TnCRA and TnCRB registers control the high and low
time of the signal produced on TAn. In PWM mode, timer/counter 2 can be used either as a simple system timer or as an
external event counter. The counter can be loaded by software with a specific value; the counter can then generate an in-
terrupt after the pre-programed number of external events have been received on TBn input.
Figure 46 shows a block diagram of the timer operating in mode 1. In PWM mode, counter 1, TnCNT1, functions as the time
base for the PWM timer. Counter 1 counts down at the clock rate selected via the counter 1 clock selector. When an under-
flow occurs, the timer register is reloaded alternately from the TnCRA and TnCRB registers, and counting proceeds down-
ward from the loaded value. On reset, and every time this mode is entered, the first reload in this mode is from the TnCRA
register. Once enabled, the counter starts counting down from the value currently in TnCNT1. At the first underflow, the timer
is loaded from TnCRA; on the second underflow, it is loaded from TnCRB; on the third underflow, it is loaded from TnCRA,
and so on. Note that every time the counter is stopped through the selection of “No-Clock” in the counter 1 clock selector
(TnCKC), it obtains its first reload value after it has been re-started from TnCRA register.
The timer can be configured to toggle TAn output bit on underflow. This results in the generation of a clock signal on TAn,
with the width and duty cycle controlled by the values stored in TnCRA and TnCRB registers. This PWM clock is processor-
independent because once the timer is set up, no more interaction is required by software (and therefore the CPU) to gen-
erate a continuous PWM signal. Software can select the initial value of the PWM output signal as either high or low. See
“Timer I/O Functions” on page 137 for additional details. The timer can be configured to generate separate interrupts on re-
load from TnCRA and TnCRB. The interrupts can be enabled or disabled under software control. The TAnPND or TnBPND
flags, respectively, which are set by the hardware on occurrence of a timer reload, indicate which interrupt occurred. See
Section 4.7.4 on page 136 for detailed information.
Mode
• No clock, in which case the counter is stopped
• Prescaled system clock
• External Event count based on TBn
• Pulse Accumulate mode based on TBn
• Slow Speed Clock (LFCLK) i.e., 32.768 KHz
1
2
3
4
Timer/Counter and Action Unit
Dual input capture
PWM and system
Input capture and
Dual independent
and system timer
timer or external
event counter
Description
timer
timer
16
to FFFF
16
). In addition, it contains the mode control logic which allows the timer to operate in any of
Time base for first
Time base for first
Counter for PWM
Timer/Counter 1
Capture A and B
(TnCNT1)
time base
timer
timer
Table 17. Operation Modes
(Continued)
value on TAn event
Reload/Capture A
Reload register for
Reload register for
Capture counter 1
Auto Reload A =
timer/counter 1
timer/counter 1
PWM time 1
132
(TnCRA)
Auto reload = PWM
value on TBn event
value on TBn event
Reload/Capture B
Reload register for
Capture counter 1
Capture counter 1
timer/counter 2
(TnCRB)
time 2
Capture B time base
System Timer or ex-
ternal event counter
Timer/Counter 2
System Timer
Time base for
second timer
(TnCNT2)
Revision 1.2