pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 161

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
4.0 Embedded Controller Modules
4.10.2 Functional Description
Input Clock
The TWD bases all its counting activities on a 32.768 KHz clock (LFCLK). The watchdog can count using a division of the
32 KHz clock (either T0OUT or T0IN).
Pre-Scale
A pre-scale counter divides the LFCLK input clock (32.768 KHz) by a factor of 2
of 0 through 5 (i.e., divide ratio of 1:1 through 1:32). The pre-scaled output is used as an input clock for a 16-bit timer
(TWDT0) and is referred to as T0IN.
TWD Timer 0
TWD Timer 0 is a 16-bit, programmable, automatically re-triggered down-counter. It counts on the rising edge of T0IN. It starts
from the value loaded to TWDT0 register down to zero and then restarts counting from TWDT0 at the next T0IN cycle.
When the counter reaches 0, T0OUT is set (1) for one T0IN cycle. This makes the Timer 0 cycle:
T0OUT is input to the ICU and can be used as the time base for activities such as system tick.
When TWDT0 is loaded with a new value, the counter uses it the next time it restarts counting (i.e., after reaching zero). If
RST in Timer Control register (T0CSR) is written 1, the timer is restarted on the next rising edge of T0IN.
Notes:
Watchdog Operation
The watchdog is an 8-bit down counter, operating on the rising edge of its currently selected clock source. On reset, it is
disabled (i.e., it does not count and no watchdog signal is generated). A write to the Watchdog Count register (WDCNT) or
the Watchdog Service Data Match (WDSDM) register either starts the counter or, if watchdog is already running, performs
a restart (“touch”) operation. Once the watchdog is counting down, only a reset can stop it.
Writing to WDCNT register is enabled while LWDCNT in TWCFG register is 0. A write to WDCNT starts the watchdog, and
it begins counting down from the written value. If the service on data match is enabled (WDSDME in TWCFG register is 1),
writing to WDSDM register with 5C
A watchdog signal is triggered if one of the following occurs:
Watchdog Clock Source Selection
Select the clock source as follows:
Changing the watchdog clock source may cause it to gain or lose one clock cycle.
Notes:
TWD Control and Configuration
The TWD Configuration register (TWCFG) allows you to:
• RST bit in T0CSR register is cleared after completing this load.
• When MDIV in TWCP register is 0, the timer counter may skip one count when loaded with a new value.
• The counter reaches zero (too late service).
• The watchdog is written to more than once per watchdog clock cycle for the currently selected clock (too early ser-
• Data other than 5C
• WDCT01 bit in TWCFG register is 0:
• WDCT01 bit in TWCFG register is 1:
• When MDIV in TWCP register is 0, the watchdog timer may skip one count when loaded with a new value.
• After activating watchdog, avoid entering Idle mode in the first four low-frequency clock cycles.
• Set the watchdog clock source: T0IN or T0OUT
• Enable watchdog service on write to WDSDM register
• Define which of TWCFG, TWCPR, TWDT0, T0CSR and WDCNT is locked.
vice). Writing to the watchdog more than once per three watchdog clock cycles (for the currently selected clock) may
cause the watchdog signal to trigger.
(TWDT0 + 1) x T0IN-cycle.
16
is written to WDSDM when WDSDME in TWCFG register is 1.
16
restarts the watchdog timer from the value stored in WDCNT.
T0OUT
T0IN
(Continued)
161
MDIV
. MDIV in TWCP register is in the range
www.national.com