pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 34

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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1.0 Introduction
Figure 7 shows the Expansion Memory Address Range mapping to the core in the PC87591L-N05 device.
External Memory Mapping into Shared BIOS Memory
When the shared BIOS memory is enabled using the SHBM strap input (SHBM=1) or the Shared Memory configuration reg-
isters (LDN=10h), the expansion memory address range is mapped into the address range of the host. The PC87591L-N05
uses the wrap-around effect of the core address space (on a 2 Mbyte boundary) using “growing down” addresses, which
enables the host to view the Expansion flash as a continuation of the BIOS Memory. See Section 5.3.2 on page 262 for de-
tails of the memory mapping scheme.
Accessing I/O Expansion Space
The I/O expansion protocol enables implementing I/O devices or GPIO ports in the system, in addition to those available on-
chip, for IRE, OBD and DEV environments. In addition, in DEV environment, some of the on-chip I/O port pins are used to
interface with off-chip peripherals. In such a case, the I/O expansion protocol is used to implement the functionality of these
I/O ports, using off-chip external logic. Access to these ports is through the same addresses used for the ports’ on-chip im-
plementation.
The I/O expansion space is mapped to the address space 00 FB00
The PC87591L-N05 accesses the off-chip I/O expansion using the I/O zone of the BIU. The zone select signal (SELIO), ad-
dress lines A0-7 and the RD and WR0 signals are used to interface to the off-chip logic.
1.5.2
The host address space includes memory space and I/O space.
The I/O space used by the PC87591L-N05 is configured through the PC87591L-N05 configuration registers. The configura-
tion register address is defined by strap inputs (BADDR0-1) to be one of two fixed addresses or an address defined by the
core using registers in the MSWC module.
When a Shared BIOS scheme is enabled via the SHBM strap input, the PC87591L-N05 is mapped to enable the host to boot
from a shared flash device. The PC87591L-N05 supports either memory or FWH transactions for the host memory interface,
with automatic selection between them (see Section 6.1.11 on page 311). Section 5.3 on page 262 discusses the mapping
of memory between the host and core domains and the read and write access protection scheme from the host and core
sides.
• Addresses in the range 00 FB00
• Address 00 FBFE
• Addresses in the range 00 FBC0
• All other addresses may be used by the application for adding additional I/O elements.
or in their off-chip implementation, while the chip is in DEV environment).
to the MCFG with the same data written to the MCFG.
64 K
Host Address Domain Memory Map
2 M
4 K
0
Core Address Map
Figure 7. Expansion Memory (Zone 0 and Zone 2) Address Range
16
(Continued)
is used only in DEV environment by the MCFGSH register and must be written after each write
16
16
to 00 FB22
to 00 FBFF
16
16
Expansion Memory Address
are used by GPIO ports PH, PI, PJ, PK, PL and PM (either on-chip
are reserved for development board use.
34
16
to 00 FBFF
2 M
0
00 DFFF - 03 FFFF
01 0000 - 04 0000
Zone 2 is enabled
16
1F FFFF
00 1000
. This space is partitioned as follows:
Access Time
Access Time
Zone 0
Control
Zone 2
Control
Zone 2 is disabled
1F FFFF
00 1000
Access Time
Zone 0
Control
Revision 1.2