pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 92

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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4.0 Embedded Controller Modules
Block Length Counter Register (BLTCn)
A double-word, read/write register. Holds the current number of DMA transfers to be executed in the current block. BLTCn
is decremented by one after each transfer cycle. A DMA transfer may consist of one or two bytes according to TCS bit in
DMACNTLn register.
Location: Channel 0 - 00 FA10
Type:
Note: Writing 0 to Block Length Counter field of BLTCn initializes the DMA for 2
Block Length Register (BLTRn)
A double-word, read/write register. Holds the number of DMA transfers to be executed in the next block. Writing this register,
sets VLD bit in DMASTATn register to 1.
Location: Channel 0 - 00 FA14
Type:
Note: Writing 0 to Block Length field of BLTRn initializes the DMA for 2
DMA Control Register (DMACNTLn)
A word-wide, read/write register that synchronizes the channel’s operation with the programing of the block transfer param-
eters. On reset, the implemented bits are initialized to 0.
The format of the DMACNTLn register is shown below.
Location: Channel 0 - 00 FA1C
Type:
Bit
Name
Bit
Name
Bit
Name
Reset
Bit
Name
Reset
Bit
0
CHEN (Channel Enable). This bit must be set to enable DMA operation on this channel
0: Channel disabled (default)
1: Channel enabled
If CHEN bit in DMACNTLn register is cleared in all channels, the DMA clock is disabled to preserve power.
Channel 1 - 00 FA30
Channel 2 - 00 FA50
Channel 3 - 00 FA70
R/W
Channel 1 - 00 FA34
Channel 2 - 00 FA54
Channel 3 - 00 FA74
R/W
Channel 1 - 00 FA3C
Channel 2 - 00 FA5C
Channel 3 - 00 FA7C
R/W
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
BPC
15
7
0
16
16
16
16
16
16
16
16
16
16
16
16
OT
14
0
6
0
Reserved
Reserved
INCB
DIR
13
0
5
0
(Continued)
ADB
Description
IND
92
12
0
4
0
21
TCS
-1 transfers.
11
0
3
0
INCA
21
-1 transfers.
Block Length Counter
EOVR
10
0
2
0
Block Length
ADA
ETC
9
0
1
0
SWRQ
CHEN
8
0
0
0
Revision 1.2