pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 268

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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5.0 Host Controller Interface Module
5.3.6
For memory update operations, the host may need to exchange signals (indicating the state) with the core. The Signaling
interface supports this scheme. The scheme is designed mainly for polling-based operations, but it allows the host to inter-
rupt the core.
The signaling hardware includes an 8-bit register that may be read by both host and core. The host may modify bits 0 through
3 of this register; the core may modify bits 4 through 7. A host write to the register sets the Host Semaphore Write (HSEMW)
bit in the Shared Memory Core Control and Status register (SMCCST); if the interrupt enable bit (HSEMIE in SMCCST reg-
ister) is set, the shared memory interrupt to the core is set.
5.3.7
The following set of registers is accessible only by the host. The registers are maintained by V
For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 32.
Shared Memory Host Register Map
Shared Memory Indirect Memory Address Register 0 (SMIMA0)
This register defines the addresses 7-0 for a read or write transaction to the memory.
Location: Offset 00
Type:
Bit
Name
7-0
Bit
Signaling Interface
Shared Memory Host Registers
Indirect Memory Address 7-0.
R/W
Offset
0C
00
01
02
03
04
07
08
16
16
16
16
16
16
16
16
16
7
SMIMA0
SMIMA1
SMIMA2
SMIMA3
SMIMD
SMHAP1
SMHAP2
SMHSEM
Mnemonic
Core Side
6
Shared Memory Indirect Memory Address 0
Shared Memory Indirect Memory Address 1
Shared Memory Indirect Memory Address 2
Shared Memory Indirect Memory Address 3
Shared Memory Indirect Memory Data
Shared Memory Host Access Protect 1
Shared Memory Host Access Protect 2
Shared Memory Host Semaphore
Figure 94. Signaling Interface
5
Indirect Memory Address 7-0
(Continued)
CSEM(3-0)
HSEM(3-0)
HSEMW
Register Name
Description
268
4
Writes
3
Host Side
2
DD
Varies per bit
Varies per bit
Varies per bit
.
Type
R/W
R/W
R/W
R/W
R/W
1
0
Revision 1.2