pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 126

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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4.0 Embedded Controller Modules
PS/2 Data Register (PSDAT)
The PSDAT register is a byte-wide read/write register. In Receive mode, PSDAT holds the data received in the last message
from the PS/2 device. In Transmit mode, the data to be shifted out is written to this register. When the PS/2 i/f is reset, the
contents of this register become invalid.
On reset, the PS/2 interface is set to Receive mode. In this mode, PSDAT should be read only when EOT bit in PSTAT
register is set to 1.
Setting the transmit enable bit in PSCON register to 1 (XMT = 1 in PSCON register) puts the PS/2 interface in Transmit
mode. PSDAT should be written only when in Transmit mode and when all four channel enable bits CLK4-1 in PSOSIG reg-
ister are cleared (0).
Location: 00 FE80
Type:
PS/2 Status Register (PSTAT)
The PSTAT register is a byte-wide read-only register. It contains the status information on the data transfer on the PS/2
ports. All non-reserved bits of PSTAT are cleared (0) on reset when CLK1, CLK2 and CLK3 in PSOSIG are cleared and
when EN bit in PSCON register is cleared. Reading PSTAT does not clear any of its bits.
Location: 00 FE82
Type:
Bit
Name
Bit
Name
Reset
7-0
5-3
Bit
Bit
0
1
2
6
7
Data. Contains the data received in the last message (or that is transmitted in the following transmission). Bit 0
is the first bit to be shifted (LSB).
SOT (Start of Transaction). When set to 1, indicates that a start bit was detected. The ACH field (bits 5-3 of
this register) indicates which of the channels it was detected on.
EOT (End of Transaction). When set to 1, Indicates that a PS/2 data transfer was completed, i.e., a stop bit
was detected at Receive mode or a line control bit was detected at Transmit mode.
PERR (Parity Error).
When set to 1, indicates that a parity error was detected in the last data transfer.
ACH (Active Channel). Defines which of the PS/2 channels is currently active (i.e., a start bit was detected). In
case more than one channel become active simultaneously, only the one with the highest priority (lowest
number) is flagged.
Bits
5 4 3 Description
0 0 0: None of the channels is active (default)
0 0 1: Channel 1
0 1 0: Channel 2
1 0 0: Channel 3
1 0 1: Channel 4
RFERR (Receive Frame Error).
When set to 1, indicates that the stop bit in a received frame was detected low instead of high.
Reserved.
R/W
RO
Reserved
16
16
7
7
x
RFERR
6
6
0
5
5
0
(Continued)
ACH
Description
Description
126
4
4
0
Data
3
3
0
PERR
2
2
0
EOT
1
1
0
SOT
0
0
0
Revision 1.2