pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 16

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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Table of Contents
5.3
5.4
5.5
5.2.3
SHARED MEMORY AND PROTECTION ............................................................................... 262
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
CORE ACCESS TO HOST-CONTROLLED MODULES ......................................................... 275
5.4.1
MOBILE SYSTEM WAKE-UP CONTROL (MSWC) ................................................................ 280
5.5.1
5.5.2
Core PM Registers .................................................................................................... 256
Memory Mapping and Host Address Translation ...................................................... 262
Indirect Memory Read and Write Transaction ........................................................... 265
Locking Between Domains ........................................................................................ 265
Host Access Protection ............................................................................................. 266
Signaling Interface ..................................................................................................... 268
Shared Memory Host Registers ................................................................................ 268
Shared Memory Core Registers ................................................................................ 271
Usage Hints ............................................................................................................... 274
Core Access to Host-Controlled Module Registers ................................................... 276
Features .................................................................................................................... 280
Wake-Up Event Detection and Status Bits ................................................................ 280
Host Bus to Core Bus Access Translation ................................................................ 262
(Continued)
Host Addresses .................................................................................................... 252
Core Interrupts ..................................................................................................... 252
Host Interrupt Generation Modes ......................................................................... 253
Status Read .......................................................................................................... 255
Host Data Read from Host Interface Power Management Channel ..................... 255
Core PM Register Map ......................................................................................... 256
Host Interface PM n Status Register (HIPMnST) ................................................. 256
Host Interface PM n Data Out Buffer (HIPMnDO) ................................................ 257
Host Interface PM n Data Out Buffer with SCI (HIPMnDOC) ............................... 257
Host Interface PM n Data Out Buffer with SMI (HIPMnDOM) .............................. 257
Host Interface PM n Data In Buffer (HIPMnDI) .................................................... 258
Host Interface PM n Data In Buffer with SCI (HIPMnDIC) ................................... 258
Host Interface PM n Control Register (HIPMnCTL) ............................................. 259
Host Interface PM n Interrupt Control Register (HIPMnIC) .................................. 260
Host Interface PM n Interrupt Enable Register (HIPMnIE) ................................... 261
Response to a Restricted Access ........................................................................ 267
Shared Memory Indirect Memory Address Register 0 (SMIMA0) ........................ 268
Shared Memory Indirect Memory Address Register 1 (SMIMA1) ........................ 269
Shared Memory Indirect Memory Address Register 2 (SMIMA2) ........................ 269
Shared Memory Indirect Memory Address Register 3 (SMIMA3) ........................ 269
Shared Memory Indirect Memory Data Register (SMIMD) ................................... 269
Shared Memory Host Access Protect Register 1 and 2 (SMHAP1-2) .................. 270
Shared Memory Host Semaphore Register (SMHSEM) ...................................... 270
Shared Memory Core Control and Status Register (SMCCST) ........................... 271
Shared Memory Core Top Address Register (SMCTA) ....................................... 272
Shared Memory Host Semaphore Register (SMHSEM) ...................................... 272
Shared Memory Core Override Read Protect Registers 0-2 (SMCORP0-2) ....... 272
Shared Memory Core Override Write Protect Registers 0-2 (SMCOWP0-2) ....... 273
Indirect Host I/O Address Register (IHIOA) .......................................................... 276
Indirect Host Data Register (IHD) ......................................................................... 276
Lock SuperI/O Host Access Register (LKSIOHA) ................................................ 277
SuperI/O Access Lock Violation Register (SIOLV) ............................................... 277
Core to SIB Modules Access Enable Register (CRSMAE) .................................. 278
SIB Control Register (SIBCTRL) .......................................................................... 279
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Revision 1.2