pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 285

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
5.0 Host Controller Interface Module
GA20 Pin Functionality
The GA20 (Gate Address A20) function is part of the PC architecture. In PC87591L-N05, the GA20 function is implemented
by a GPIO signal that is configured as output. Port PB5 is recommended to be used as GA20 since its default state after
reset is output driving high. The firmware running on the core may change the GA20 signal state by modifying bit 5 in PBD-
OUT register. There is no special hardware or multiplexing on PB5; since there is no multiplexing, bit 5 of PBALT register is
always 0 and any writes to it are disregarded. PB5 may be used as a GPIO; however, note that wake-up for PB5 differs from
the other signals in port B.
5.5.5
The MSWC registers are organized in four banks, all of which are battery-backed. The offsets are related to a base address
that is determined by the MSWC Base Address register in the device configuration registers. The lower 19 offsets (00
12
The active bank is selected through the Configuration Bank Select field (bits 1-0) in the Wake-Up Configuration register
(WK_CFG).
As a programing aid, the registers are described in this chapter according to the following functional groupings:
For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 32.
MSWC Host Register Map
The following tables list the MSWC host registers. For the MSWC core register map, see Section 5.5.6 on page 291.
• Bank 0 is reserved.
• Bank 1 is reserved.
• Bank 2 holds the Event Routing Configuration and Wake-Up Extension Control registers.
• Bank 3 is reserved.
• General status
• Enable
• Configuration
• Routing
16
) are common to the four banks; the upper offsets (13
MSWC Host Registers
Offset
Offset
Other
Other
00
02
04
06
07
13
15
16
16
16
16
16
16
16
Table 34. Banks 0, 1, 2 and 3 - The Common Control and Status Register Map
WK_STS0
WK_EN0
WK_CFG
WK_SIGV
WK_STATE
Reserved
WK_SMIEN0
WK_IRQEN0
Reserved
Table 35. Bank 2 - Event Routing Configuration Register Map
Mnemonic
Mnemonic
Wake-Up Event Status 0
Wake-Up Enable 0
Wake-Up Configuration
Wake-Up Signal Value
Wake-Up ACPI State
Wake-Up SMI Enable 0
Wake-Up Interrupt Request Enable 0
(Continued)
16
285
-1F
16
Register Name
Register Name
) are divided as follows:
R/W1C
Type
Type
R/W
R/W
R/W
R/W
WO
RO
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