pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 262

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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5.0 Host Controller Interface Module
5.3
The PC87591L-N05 off-chip expansion memory can be shared by the host and the core. It may also be used by the host for
BIOS code storage or other purposes. The off-chip expansion memory resides in the core domain. In IRE and OBD environ-
ments, it is accessible via the core bus. For host accesses, the expansion memory is mapped to the host memory address
space via the host interface, and a bridge is provided between the host bus and the core bus. The bridge functionality includes:
5.3.1
A core bus transaction is generated for each of the following types of host bus transactions:
Memory and FWH memory read/write transactions drive Long Wait on the Sync field until the transaction is completed on
the core bus. Section 5.3.3 on page 265 describes the Sync field for indirect memory read/write transactions. Section 5.3.5
on page 266 describes the behavior for restricted accesses.
The host bus transaction is forwarded to the core bus after the following is done:
Note that host bus read transactions are translated to read transactions on the core bus, and host bus write transactions are
translated to write transactions on the core bus. Translated reads and writes behave the same as reads and writes by the core.
5.3.2
Section 6.1.11 on page 311 describes in detail the host domain addresses for which the core bus generates transactions. In
general, the BIOS memory on the host bus can occupy one of three regions in the memory space (see Table 50 on page 311).
Address translation between the host and the core domains is performed for host memory and FWH memory transactions.
The 32-bit address received from the host bus is used to decode the different zones, as described in Section 6.1.11 on
page 311. The address is then translated to the core bus address using the following rules:
• Memory mapping between host domain address space and core domain address space
• Host bus to core bus transaction bridging
• Locking mechanism between host and core domains to maintain coherence of off-chip expansion memory contents
• Read/write protection on host accesses to the off-chip expansion memory
• Host-accessible control and status registers of off-chip expansion memory
• Signaling interface for host-core communication associated with memory updates
• 8-bit memory read/write
• 8-bit FWH memory read/write
• 8-bit indirect read/write transactions, using I/O read/write to access the shared expansion memory (see Section 5.3.3
• Address is translated.
• The translated address and the access type are verified to be both:
• For writes, the HLOCK bit in SMCCST register must be set.
• Legacy and Extended Legacy BIOS Range
• User Defined Shared Memory Space
• 386 Mode-Compatible BIOS Range
• Indirect Memory Address
during updates
on page 265)
— In core domain’s expansion memory space
— Unprotected
Handle only when enabled (see Section 6.1.11 on page 311 for the enabling alternatives); otherwise, transactions to
this zone are ignored. The address is converted to a shared memory internal address as follows:
This address range is handled only when enabled (see Section 6.1.11 on page 311 for the enabling alternatives);
otherwise, transactions to this zone are ignored. The address translation depends on the window size defined. When
the window size is 2
LPC address are replaced with 1. The address is converted to an internal address as follows:
This address range is handled only when enabled (see Section 6.1.11 on page 311 for the enabling alternatives);
otherwise, transactions to this zone are ignored. The address is converted to an internal address as follows:
This address specified in IMA3-0 is used as follows:
SHARED MEMORY AND PROTECTION
Memory Mapping and Host Address Translation
Host Bus to Core Bus Access Translation
SM_Host_Address[31-0] = {1111 1111 1111 111, Host_Memory_Address[16-0]}
SM_Host_Address[31-0] = {1111 ... ... 1, Host_Memory_Address[(n-1)-0]}
SM_Host_Address[31-0] = Host_Memory_Address[31-0]
SM_Host_Address[31-0] = {IMA3[7-0], IMA2[7-0], IMA1[7-0], IMA0[7-0]}
n
bytes, the lower ‘n’ bits are taken from the memory address, and the upper 32
(Continued)
262
n bits of the
Revision 1.2