pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 162

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

www.national.com
4.0 Embedded Controller Modules
Once LTWCFG, LTWCP, LTWDT0 or LWDCNT, in TWCFG register, is set its respective resources are locked and can be
cleared only by reset. Setting any of these registers prevents runaway software from tampering with the respective watchdog
function.
Operation in Idle Mode
The TWD is active in Idle mode: the counters continue to function, and interrupts and error signals are issued.
Write operations to TWCP, TWDT0 and WDCNT may be delayed by up to three 32.768 KHz clock cycles. The software should
avoid entering Idle mode during this period. WDTLD bit in T0CSR register indicates when it is safe to switch power modes.
4.10.3 TWD Registers
For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 32.
TWD Register Map
Timer and Watchdog Configuration Register (TWCFG)
The TWCFG register is a byte-wide, read/write register. It defines the watchdog clock input and service method and enables
TWD control register locking. Setting the required configuration and locking the TWCFG stops the software from interfering
with the watchdog operation. On reset, non-reserved bits of TWCFG are initialized to 0.
Location: 00 FEE0
Type:
Bit
Name
Reset
Bit
0
1
2
LTWCFG.
0: Enables read/write from/to TWCFG register (default)
1: Any data written to it is ignored and reading from it returns unpredictable values
Once LTWCFG is set, it can only be cleared by reset.
LTWCP.
0: Enables read/write from/to TWCP register (default)
1: Any data written to it is ignored and reading from it returns unpredictable values
Once LTWCP is set, it can only be cleared by reset.
LTWDT0.
0: Enables read/write from/to TWDT0 and T0CSR registers (default)
1: Registers cannot be written to and TWDT0 cannot be read. Any data written to TWDT0 or T0CSR is ignored.
Once LTWDT0 is set, it can only be cleared by reset.
R/W
Reading from TWDT0 returns unpredictable values.
TWCFG
TWCP
TWDT0
T0CSR
WDCNT
WDSDM
Mnemonic
16
7
0
Reserved
Timer and Watchdog Configuration Register
Timer and Watchdog Clock Pre-Scaler Register
TWD Timer 0 Register
TWDT0 Control and Status Register
Watchdog Count Register
Watchdog Service Data Match Register
6
0
WDSDME
5
0
(Continued)
Register Name
WDCT0I
Description
162
4
0
LWDCNT
3
0
LTWDT0
2
0
Type
R/W
R/W
R/W
R/W
WO
WO
LTWCP
1
0
LTWCFG
0
0
Revision 1.2