pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 297

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
6.0 Host-Controlled Modules and Host Interface
6.1
The PC87591L-N05 Host-Controlled Functions comprises a collection of generic and proprietary functional blocks. Each
functional block is described in a separate section in this document. However, some parameters in the implementation of
the functional blocks may vary per function and/or device. This chapter describes the PC87591L-N05 structure and provides
all logical device-specific information, including special implementation of generic blocks, system interface and device con-
figuration.
The PC87591L-N05 Host-Controlled Functions consist of seven logical devices (involving six modules), the host interface
and a central set of configuration registers, all built around a central internal bus. The internal bus is similar to an 8-bit ISA
bus protocol. Figure 100 shows the blocks and their interconnection.
The LPC Bus Interface serves as a bridge between the external LPC interface and the internal bus. It supports the following
operations, as defined in Intel’s LPC Interface Specification, Revision 1.0:
The Configuration and Control register set supports ACPI-compliant PnP configuration. The configuration registers are
structured as a subset of the Plug and Play Standard registers, defined in Appendix A of the Plug and Play ISA Specification,
Revision 1.0a by Intel and Microsoft, and are similar to those used in National SuperI/O devices. All system resources as-
signed to the functional blocks (I/O address space, and IRQ lines) are configured in and managed by this register set. In
addition, some function-specific parameters are configurable through the configuration registers and distributed to the func-
tional blocks through special control signals.
6.1.1
The configuration structure comprises a set of banked registers that are accessed via a pair of specialized registers.
The Index-Data Register Pair
Access to the Host-Controlled Functions configuration registers is via an Index-Data register pair, using two system I/O byte
locations. The base address of this register pair is determined during V
ware strapping option on the BADDR1-0 pins. Table 37 shows the selected base addresses as a function of BADDR1-0 (see
Section 2.2.11 on page 45).
The Index register is an 8-bit read/write register located at the selected base address (Base+0). It is used as a pointer to the
configuration register file and holds the index of the configuration register that is currently accessible via the Data register.
Reading the Index register returns the last value written to it (or a default of 00
The Data register is an 8-bit register located at the selected base address (Base+1) used as a data path to any configuration
register. Accessing the Data register actually accesses the configuration register that the Index register is currently pointed to.
• 8-bit I/O read
• 8-bit I/O write
• 8-bit Memory read
• 8-bit Memory write
• 8-bit FWH read
• 8-bit FWH write
DEVICE ARCHITECTURE AND CONFIGURATION
Configuration Structure and Access
BADDR1-0
1. See “Host Configuration Address Selection” on page 284 for more
1 0
0 0
0 1
1 1
details about this option.
1
(HCFGBAH,HCFGBAL)
Table 37. BADDR1-0 Strapping Options
Index Register
2E
4E
16
16
XOR-Tree Test Mode
297
I/O Address
CC
(HCFGBAH,HCFGBAL)+1
Power-Up reset, according to the state of the hard-
Data Register
16
after Host Domain reset).
2F
4F
16
16
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