pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 171

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
4.0 Embedded Controller Modules
4.11.5 ADC Registers
The ADC control/status and data out registers set interfaces with the core through the Peripheral bus. These registers are
mapped in the address space of the core, starting at the base address defined in Appendix 61 on page 393.
For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 32.
ADC Register Map
The ADC register set contains six common, control and status registers and six channel-specific registers.
ADC Status Register (ADCSTS)
This register indicates the global status of the ADC module. ADCSTS is cleared (00
resets, bit 2 is unchanged and other bits are cleared.
Location: 00 FF20
Type:
Bit
Name
Warm Reset
Power-Up
Reset
7-2
Bit
0
1
R/W1C OVFEV (Data Overflow Event). Measurement data from the previous cycle was overwritten with data
Type
RO
Varies per bit
EOCEV (End-of-Cycle Event). End of ADC cycle; all enabled measurements (up to four) are
completed. For each of the enabled channels, the DATVAL bit in the respective VCHNxCTL register is
set, and the data for the channel is stored in the respective Channel Data Buffer register.
0: Cycle in progress (default)
1: End of ADC cycle (the bit remains set until all DATVAL bits in the Channel Control registers are reset)
from the current cycle before being read. In the event of a data overflow, the DATVAL bit remains set
and new data is placed in Channel Data Buffer register.
0: No overflow (default)
1: Overflow
Reserved.
16
7
0
0
ADCSTS
ADCCNF
ACLKCTL
ADLYCTL
ADCPINX
ADCPD
VCHN1CTL
VCHN1DAT
VCHN2CTL
VCHN2DAT
VCHN3CTL
VCHN3DAT
Mnemonic
6
0
0
ADC Status
ADC Configuration
ADC Clock Control
ADC Delay Control
ADC Parameters Index
ADC Parameters Data
Voltage Channel 1 Control
Voltage Channel 1 Data Buffer
Voltage Channel 2 Control
Voltage Channel 2 Data Buffer
Voltage Channel 3 Control
Voltage Channel 3 Data Buffer
Table 22. ADC Register Map
5
0
0
Reserved
(Continued)
Register Name
171
4
0
0
Description
3
0
0
16
Varies per bit
Varies per bit
Varies per bit
Varies per bit
) on V
2
0
-
Type
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
CC
Power-Up reset; on other
OVFEV
1
0
0
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EOCEV
0
0
0