pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 303

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
6.0 Host-Controlled Modules and Host Interface
Standard Configuration
The standard configuration registers manage the PnP resource allocation to the functional blocks. The I/O port base address
(descriptor 0) is a pair of registers at index 60-61
block. An optional 16-bit second base-address (descriptor 1) at index 62-63
continuous register set. Interrupt Number and Wake-Up on IRQ Enable (index 70
isters allocate an IRQ number to the module’s interrupt and control the interrupt type and polarity. DMA Channel Select 0
(index 74
DMA channel, where applicable.
Special Configuration
The vendor-defined registers, starting at index F0
power saving modes, clock rate selection and non-standard extensions to generic functions.
6.1.3
The default configuration setup of the PC87591L-N05 Host-Controlled functions is set according to the following reset types
(see Section 3.2 on page 61):
If a Host Domain Hardware reset occurs, the PC87591L-N05 wakes up with the following default SuperI/O configuration setup:
If a Host Domain reset occurs (either Software or Hardware), the PC87591L-N05 wakes up with the following default Su-
perI/O configuration setup:
6.1.4
A full 16-bit address decoding is applied when accessing the configuration I/O space as well as the registers of the functional
blocks. However, the number of configurable bits in the base address registers varies for each logical device.
The lower 0, 1, 2, 3, 4 or 5 address bits are decoded within the functional block to determine the offset of the accessed reg-
ister within the logical device’s I/O range of 1, 2, 4, 8, 16 or 32 bytes, respectively. The rest of the bits are matched with the
base address register to decode the entire I/O range allocated to the logical device. Therefore, the lower bits of the base
address register are forced to 0 (read only), and the base address is forced to be 1, 2, 4, 8, 16 or 32 byte-aligned, according
to the size of the I/O range.
The base address of the KBC, PM channel 1 and PM channel 2 are limited to the I/O address range of 0000
only (bits 11-15 are forced to 0). The addresses of other devices are configurable within the full 16-bit address range (up to
FFFF
In some special cases, other address bits are used for internal decoding (such as bit 2 in the KBC). The KBC has two I/O
descriptors with some implied dependency between them. For more details, see the description of the base address register
for each logical device.
The Shared Memory and Protection module serves as a bridge from the LPC to the on-chip ROM and off-chip expansion
memory. For module control and protection function registers, the 16-bit base address is applied through the configuration
address space. To access the registers, the lower four address bits are decoded within the Shared Memory module. The
address ranges in the LPC memory space and the FWH memory space, which are bridged to the shared memory, are de-
• V
• V
• Host Domain Hardware Reset
• Host Domain Software Reset
Resets V
V
Resets the MSWC registers whose values are retained by V
— Resets all SuperI/O logical devices, with the exception of the Mobile System Wake-Up Control (MSWC) and the RTC
— Resets all SuperI/O configuration registers.
— Resets all SuperI/O logical devices, except the MSWC and the RTC registers retained by V
— Resets most bits in the SuperI/O configuration registers. This reset does not affect register bits that are locked for
— The configuration base address is according to the BADDR strap pin value, as shown in Table 37 on page 297.
— All logical devices are disabled, with the exception of the MSWC and shared memory, which remain functional but
— The legacy devices are assigned with their legacy system resource allocation.
— The National proprietary functions are not assigned with any default resources, and the default values of their base
PP
PP
CC
16
.
registers retained by V
write access (see “SuperI/O Configuration 6 Register (SIOCF6)” on page 308 and Table 37 on page 297).
whose registers cannot be accessed.
addresses are all 00
).
Power-Up Reset
Default Configuration Setup
Power-Up Reset
Address Decoding
16
) allocates a DMA channel to the block, where applicable. DMA Channel Select 1 (index 75
PP
-retained SuperI/O functions, such as the RTC and the MSWC registers, whose values are retained by
16
.
PP
or V
CC
.
16
16
, holding the first 16-bit base address for the register set of the functional
- F9
16
, control function-specific parameters such as operation modes,
303
CC
only.
(Continued)
16
is used for logical devices with more than one
16
) and IRQ Type Select (index 71
PP
16
or V
) allocates a second
CC
.
16
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to 07FX
16
) reg-
16