MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 90

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Functional Description
Parallel scans differ in that converter A performs up to eight samples (SAMPLE[0:3],
SAMPLE[8:11]) in parallel with converter B (SAMPLE[4:7], SAMPLE[12:15]).
Constraints are as follows:
Within these constraints, any sample can reference any pin, and more than one sample
slot can reference the same sample and the same input. Only SAMPLE[0:7] have the full
functionality of offset subtraction and high/low limit compare. By default (when
CTRL2[SIMULT]=1), the scans in both converters are initiated when the
CTRL1[START0] bit is written with a 1 or when the CTRL1[SYNC0] bit has a value of
1 and the SYNC0 input goes high. The scan in both converters terminates when either
converter encounters a disabled sample slot. Completion of a scan triggers the
STAT[EOSI0] interrupt if the CTRL1[EOSIEN0] interrupt enable is set. Samples are
always taken simultaneously in both the A and B converters. Setting the CTRL1 [STOP0]
bit stops and prevents the initiation of scanning in both converters.
Setting CTRL2[SIMULT]=0 (non-simultaneous mode) causes parallel scanning to
operate independently in the A and B converter. Each converter has its own set of
START, STOP, SYNC, and EOSIEN control bits, SYNC input, EOSI interrupt, and CIP
status indicators (suffix 0 for converter A and suffix 1 for converter B). Though still
operating in parallel, the scans in the A and B converter start and stop independently
according to their own controls and can be simultaneous, phase shifted, or asynchronous
depending on when scans are initiated on the respective converters. The A and B
converters can be of different length (still up to a maximum of 8) and each converter's
scan completes when a disabled sample is encountered in that converters sample list only.
CTRL1[STOP0] stops the A converter only and CTRL2[STOP1] stops the B converter
only. Looping scan modes iterate independently. Each converter independently restarts its
scan after completing its list or encountering a disabled sample slot.
2.4.5 Scan Sequencing
The sequential and parallel scan modes fall into three types based on how they repeat:
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• SAMPLEs[0:3] and SAMPLEs[8:11] can reference only the ANA[0:7] inputs.
• SAMPLEs[4:7] and SAMPLEs12:15] can reference only the ANB[0:7] inputs.
• Once scan. A once scan executes a sequential or parallel scan only once each time it
• Triggered scan. Identical to the corresponding once scan modes except that resetting
• Looping scan. Automatically restarts a scan, either parallel or sequential, as soon as
is started. It differs from a triggered scan in that sync inputs must be re-armed after
each use.
CTRL*[SYNC*] bits is not necessary.
the previous scan completes. In parallel looping scan modes, the A converter scan
restarts as soon as the A converter scan completes and the B converter scan restarts
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Preliminary
Freescale Semiconductor