MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 509

DSC 64K FLASH 60MHZ 64-LQFP

MC56F8257MLH

Manufacturer Part Number
MC56F8257MLH
Description
DSC 64K FLASH 60MHZ 64-LQFP
Manufacturer
Freescale Semiconductor
Series
56F8xxxr

Specifications of MC56F8257MLH

Core Processor
56800E
Core Size
16-Bit
Speed
60MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Ram Size
4K x 16
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x12b, D/A 1x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
64-LQFP
Product
DSCs
Processor Series
56800E
Core
56800E
Device Million Instructions Per Second
60 MIPs
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
54
Data Ram Size
8 KB
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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When an interrupt occurs, its vector number is compared with the FIM0 and FIM1
register values. If a match occurs, and if the interrupt priority is level 2, the INTC handles
the interrupt as a fast interrupt. The INTC takes the vector address from the appropriate
FIVALn and FIVAHn registers, instead of generating an address that is an offset from the
vector base address (VBA).
The core then fetches the instruction from the indicated vector address. If the instruction
is not a JSR, the core starts its fast interrupt handling.
14.4 Resets
14.4.1 INTC after Reset
After reset, all INTC registers are in their default states. As a result, all interrupts are
disabled except the core IRQs with fixed priorities (Illegal Instruction, SW Interrupt 3,
HW Stack Overflow, Misaligned Long Word Access, SW Interrupt 2, SW Interrupt 1,
SW Interrupt 0, and SW Interrupt LP), which are enabled at their fixed priority levels.
Freescale Semiconductor
Core reset
Reset
Priority
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Table 14-25. Reset Summary
Source
RST_B
Preliminary
Core reset from the SIM
Characteristics
Chapter 14 Interrupt Controller (INTC)
509

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