MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 556

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory Map and Registers
16.2.20 Protection Register (SIM_PROT)
SIM_PROT provides write protection of selected control fields for safety critical
applications. The primary purpose is to prevent unsafe conditions due to the unintentional
modification of these fields between the onset of a code runaway and a reset by the COP
watchdog. GPIO and Internal Peripheral Select Protection (GIPSP) write-protect the
registers in the SIM, XBAR, and GPIO modules that control inter-peripheral signal
multiplexing and I/O cell configuration. Peripheral Clock Enable Protection (PCEP) write
protects the SIM registers that contain peripheral-specific clock controls. Some
peripherals provide additional safety features.
GIPSP protects the contents of the SIM registers that control multiplexing of peripheral
signals onto GPIO (GPSn) and the XBAR registers that select among optional peripheral
inputs (CODEn). GIPSP also write protects some registers in the GPIO module, including
the GPIO_X_PER registers that select between peripheral versus GPIO ownership of the
I/O cell, the GPIO_X_PPMODE registers the control the I/O cell push/pull mode, and
GPIO_X_DRIVE registers that control the I/O cell drive strength.
PCEP write protects the SIM peripheral clock enable registers (PCEn), the SIM
peripheral stop disable registers (SDn), and the SIM peripheral clock rate registers (PCR).
For flexibility, write protection control values may themselves be optionally locked
(write protected). To this end, protection controls in this register have two bit values. The
right bit determines the setting of the control, and the left bit determines whether the
value is locked. While a protection control remains unlocked, protection can be disabled
and re-enabled as desired. When a protection control is locked, its value can be altered
only by a device reset, which restores its default non-locked value.
Address: SIM_PROT – F0E0h base + 14h offset = F0F4h
556
Reset
Read
Write
Bit
Reserved
15–4
Field
15
0
14
0
This read-only bitfield is reserved and always has the value zero.
00
01
13
Write protection off (default).
Write protection on.
0
12
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
11
0
SIM_PROT field descriptions
Table continues on the next page...
10
0
0
0
9
Preliminary
0
8
Description
0
7
0
6
0
5
0
4
0
3
Freescale Semiconductor
PCEP
0
2
0
1
GIPSP
0
0