MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 266

DSC 64K FLASH 60MHZ 64-LQFP

MC56F8257MLH

Manufacturer Part Number
MC56F8257MLH
Description
DSC 64K FLASH 60MHZ 64-LQFP
Manufacturer
Freescale Semiconductor
Series
56F8xxxr

Specifications of MC56F8257MLH

Core Processor
56800E
Core Size
16-Bit
Speed
60MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Ram Size
4K x 16
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x12b, D/A 1x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
64-LQFP
Product
DSCs
Processor Series
56800E
Core
56800E
Device Million Instructions Per Second
60 MIPs
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
54
Data Ram Size
8 KB
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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Functional Description
7.4.1.6 Enhanced Capture Capabilities (E-Capture)
When a PWM pin is not being used for PWM generation, it can be used to perform input
captures. Recall that for PWM generation BOTH edges of the PWM signal are specified
via separate compare register values. When programmed for input capture, both of these
registers work on the same pin to capture multiple edges, toggling from one to the other
in either a free running or one-shot fashion. By simply programming the desired edge of
each capture circuit, period and pulse width of an input signal can easily be measured
without the requirement to re-arm the circuit. In addition, each edge of the input signal
can clock an 8 bit counter where the counter output is compared to a user specified value
(EDGCMP). When the counter output equals EDGCMP, the value of the submodule
timer is captured and the counter is automatically reset. This feature allows the module to
count a specified number of edge events and then perform a capture and interrupt. The
following figure illustrates some of the functionality of the E-Capture circuit.
266
Output Triggers
VAL5
VAL4
VAL3
VAL2
VAL1
VAL0
Figure 7-214. Multiple Output Triggers Over Several PWM Cycles
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Submodule0 counter (PWM generation)
Submodule1 counter
Preliminary
Freescale Semiconductor

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