MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 67

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2.3.14 ADC Result Registers (ADC_RSLTn)
The result registers contain the converted results from a scan. The CLIST3[SAMPLE8]
result is loaded into RSLT8, CLIST3[SAMPLE9] result in RSLT9, and so on. In a
parallel scan mode, the first channel pair designated by CLIST3[SAMPLE8] and
CLIST4[SAMPLE12] are stored in RSLT8 and RSLT12, respectively.
Addresses: ADC_RSLT8 – F080h base + 14h offset = F094h
Freescale Semiconductor
Reset
Read
Write
Bit
Reserved
SEXT
RSLT
14–3
Field
2–0
15
15
0
0
ADC_RSLT9 – F080h base + 15h offset = F095h
ADC_RSLT10 – F080h base + 16h offset = F096h
ADC_RSLT11 – F080h base + 17h offset = F097h
ADC_RSLT12 – F080h base + 18h offset = F098h
ADC_RSLT13 – F080h base + 19h offset = F099h
ADC_RSLT14 – F080h base + 1Ah offset = F09Ah
ADC_RSLT15 – F080h base + 1Bh offset = F09Bh
14
When writing to this register, only the RSLT portion of the
value written is used.
0
Sign Extend
This is the sign-extend bit of the result. RSLT*[SEXT] set to one implies a negative result. RSLT*[SEXT]
set to zero implies a positive result. If positive results are required, then the respective offset register must
be set to a value of zero.
Digital Result of the Conversion
RSLT can be interpreted as either a signed integer or a signed fractional number. As a signed fractional
number, the RSLT can be used directly. As a signed integer, it is an option to right shift with sign extend
(ASR) three places and interpret the number, or accept the number as presented, knowing there are
missing codes. The lower three bits are always going to be zero.
Negative results, RSLT*[SEXT] = 1, are always presented in two's complement format. If it is a
requirement of your application that the result registers always be positive, the offset registers must
always be set to zero.
The interpretation of the numbers programmed into the limit and offset registers, LOLIM, HILIM, and
OFFST should match your interpretation of the result register.
This read-only bitfield is reserved and always has the value zero.
13
0
12
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
11
0
ADC_RSLTn field descriptions
10
0
0
9
Preliminary
RSLT
Note
0
8
Description
0
7
0
6
Chapter 2 Analog-to-Digital Converter (ADC)
0
5
0
4
0
3
0
2
0
0
1
0
0
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