MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 360

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory Map and Registers
Write: this register is not writable
Addresses: QSCI0_STAT – F1E0h base + 3h offset = F1E3h
360
Reset
Read TDRE
Write
Bit
TIDLE
RIDLE
TDRE
RDRF
Field
15
14
13
12
15
1
QSCI1_STAT – F1F0h base + 3h offset = F1F3h
TIDL
14
E
1
Transmit Data Register Empty Flag
This bit is set when the TX FIFO word count (CTRL2[TFCNT]) falls to the watermark level
(CTRL2[TXWM]). Clear TDRE by reading STAT with TDRE set and then writing to the SCI data register
until CTRL2[TFCNT] is above CTRL2[TFWM]. If CTRL2[FIFO_EN] or CTRL2[TDE] is set, then you can
clear TDRE by writing to the SCI data register without first reading STAT with TDRE set.
0
1
Transmitter Idle Flag
This bit is set when the TX FIFO is empty and no data, preamble, or break character is being transmitted.
When TIDLE is set, the TXD pin becomes idle (1). Clear TIDLE by reading STAT with TIDLE set and then
writing to the SCI data register. TIDLE is not generated when a data character, a preamble, or a break is
queued and ready to be sent.
0
1
Receive Data Register Full Flag
This bit is set when the RX FIFO word count (CTRL2[RFCNT]) rises above the watermark
(CTRL2[RXWM]). Clear RDRF by reading STAT with RDRF set and then reading the SCI data register
until CTRL2[RFCNT] is no longer above CTRL2[RFWM]. If CTRL2[FIFO_EN] or CTRL2[RDE] is set, then
you can clear RDRF by reading the SCI data register without first reading STAT with RDRF set.
NOTE: When you are using the CodeWarrior debugger, RDRF may be erased when a breakpoint is
0
1
Receiver Idle Line Flag
This bit is set when 10 consecutive ones (if CTRL1[M]=0) or 11 consecutive ones (if CTRL1[M]=1) appear
on the receiver input. The RIDLE flag is cleared by reading STAT with RIDLE set and then reading the
SCI data register. Once RIDLE is cleared, a valid frame must be received before an idle condition can set
RIDLE.
NOTE: When the receiver wake-up bit (CTRL1[RWU]) is set, an idle line condition does not set RIDLE.
RDRF
TX FIFO word count is above watermark
TX FIFO word count is at or below watermark
Transmission in progress
No transmission in progress
RX FIFO word count is at or below watermark
RX FIFO word count is above watermark
13
0
reached. If a memory window that includes the SCI registers is open when a breakpoint is
reached, these memory addresses are read to update the memory window. If RDRF is set at this
time, these reads satisfy the requirements for clearing RDRF because the status register is read
with RDRF set and then the data register is read, which causes RDRF to clear.
RIDL
12
E
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
OR
11
0
QSCIx_STAT field descriptions
Table continues on the next page...
NF
10
0
FE
0
9
Preliminary
PF
0
8
Description
0
7
0
0
6
0
5
0
0
4
LSE
0
3
Freescale Semiconductor
0
2
0
0
1
RAF
0
0