MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 405

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

When CPHA = 0 for a slave, the falling edge of SS indicates the beginning of the
transaction. This causes the SPI to leave its idle state and begin driving the MISO pin
with the first bit of its data. After the transaction begins, no new data is allowed into the
shift register from the transmit data register. Therefore, the SPI data register of the slave
must be loaded with transmit data before the falling edge of SS. Any data written after
the falling edge is stored in the transmit data register and transferred to the shift register
after the current transaction. Also, for correct operation of the slave, SPE must be active
before the negative edge of SS to correctly send/receive the first word. The SS line is the
slave select input to the slave. The slave SPI drives its MISO output only when its slave
select input (SS) is at logic zero, so that only the selected slave drives to the master.
When CPHA = 0 for a master, normal operation would begin by the master initializing
the SS pin of the slave high. A transfer would then begin by the master setting the SS pin
of the slave low and then writing the DXMIT register. After a data transfer completes, the
master device puts the SS pin back into the high state. While MODFEN = 1, the SS pin
of the master must be high or a mode fault error occurs. If MODFEN = 0, the state of the
SS pin is ignored.
>
12.4.2.5 Transaction Format When CPHA = 1
The following figure shows an SPI transaction in which CPHA is logic one. The figure
should not be used as a replacement for data sheet parametric information. It assumes 16
bit data lengths and the MSB shifted out first.
Freescale Semiconductor
MISO/MOSI
(CPHA = 0)
(CPHA = 1)
Master SS
Slave SS
Slave SS
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
D A T A 1
Figure 12-11. CPHA /SS Timing
Preliminary
D A T A 2
Chapter 12 Queued Serial Peripheral Interface (QSPI)
D A T A 3
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