MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 418

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Introduction
13.1.1 Block Diagram
13.1.2 Features
The basic features of the MSCAN are as follows:
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• Implementation of the CAN protocol — Version 2.0A/B
• Five receive buffers with FIFO storage scheme
• Three transmit buffers with internal prioritization using a "local priority" concept
• Flexible maskable identifier filter supports two full-size (32-bit) extended identifier
• Programmable wakeup functionality with integrated low-pass filter
Wake-Up Interrupt Req.
Transmit Interrupt Req.
Receive Interrupt Req.
filters, or four 16-bit filters, or eight 8-bit filters
Errors Interrupt Req.
• Standard and extended data frames
• Zero to eight bytes data length
• Programmable bit rate up to 1 Mbps
• Support for remote frames
Oscillator Clock
1. Depending on the actual bit timing and the clock jitter of the PLL.
Bus Clock
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
MSCAN
Figure 13-1. MSCAN Block Diagram
MUX
Configuration
CANCLK
Registers
Control
Status
and
Preliminary
Presc.
1
Tq Clk
Wake-Up
Low Pass Filter
Message
Buffering
Receive/
Transmit
Filtering
Engine
and
Freescale Semiconductor
R X C A N
TXCAN