MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 565
MC56F8257MLH
Manufacturer Part Number
MC56F8257MLH
Description
DSC 64K FLASH 60MHZ 64-LQFP
Manufacturer
Freescale Semiconductor
Series
56F8xxxr
Datasheets
1.TWR-56F8257.pdf
(88 pages)
2.MC56F8245VLD.pdf
(14 pages)
3.MC56F8245VLD.pdf
(2 pages)
4.MC56F8245VLD.pdf
(629 pages)
Specifications of MC56F8257MLH
Core Processor
56800E
Core Size
16-Bit
Speed
60MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Ram Size
4K x 16
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x12b, D/A 1x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
64-LQFP
Product
DSCs
Processor Series
56800E
Core
56800E
Device Million Instructions Per Second
60 MIPs
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
54
Data Ram Size
8 KB
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC56F8257MLH
Manufacturer:
MOTOLOLA
Quantity:
560
Company:
Part Number:
MC56F8257MLH
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- TWR-56F8257 PDF datasheet
- MC56F8245VLD PDF datasheet #2
- MC56F8245VLD PDF datasheet #3
- MC56F8245VLD PDF datasheet #4
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- Download datasheet (4Mb)
16.3.3 Stop and Wait Mode Disable Function
The DSC core contains both STOP and WAIT instructions. Both put the CPU to sleep.
The peripheral bus continues to run in wait mode, but in stop mode, only peripherals
whose SDn control is asserted continue to run. Entry into stop or wait mode does not
affect the OCCS configuration and affects only the generation of system and peripheral
clocks from the master clocks from the OCCS. The OCCS may be reconfigured prior to
entering stop or wait, if desired, to reduce master clock frequencies and thus the power
use within the OCCS.
Some applications require the DSC STOP/WAIT instructions to be disabled. Control
fields are provided in the CTRL register to disable wait and/or stop modes. This
procedure can be on either a permanent (until reset) or temporary basis.
16.4 Resets
The SIM supports several sources of reset, as shown in the following table.
Freescale Semiconductor
re-programmable disable
permanent
disable
select
clock
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
RESET
RESET
Figure 16-25. Stop Disable Circuit
>CLK
>CLK
D
D
D-FLOP
D-FLOP
Preliminary
R
R
Q
Q
Chapter 16 System Integration Module (SIM)
stop_dis
56800E
565
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