MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 403

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

device; slave devices that are not selected do not interfere with SPI bus activities. On a
master SPI device, the slave select line can optionally be used to indicate multiple-master
bus contention.
>
12.4.2.1 Data Transaction Length
The SPI can support data lengths of two to sixteen bits. This can be configured in the data
size register, DSCTRL. When the data length is less than sixteen bits, the receive data
register pads the upper bits with zeros.
>
12.4.2.2 Data Shift Ordering
The SPI can be configured to transmit or receive the MSB of the desired data first or last.
This is controlled by the data shift order, DSO, bit in the SCTRL register. Regardless of
which bit is transmitted or received first, the data shall always be written to the data
transmit register, DXMIT, and read from the receive data register, DRCV, with the LSB
in bit 0 and the MSB in correct position depending on the data transaction size.
>
12.4.2.3 Clock Phase and Polarity Controls
Software can select any of four combinations of serial clock (SCLK) phase and polarity
using two bits in the SPI control register (SCTRL). The clock polarity is specified by the
CPOL control bit, which selects an active high or low clock and has no significant effect
on the transaction format.
The clock phase (CPHA) control bit selects one of two fundamentally different
transaction formats. The clock phase and polarity should be identical for the master SPI
device and the communicating slave device. In some cases, the phase and polarity are
changed between transactions to allow a master device to communicate with peripheral
slaves having different requirements.
Freescale Semiconductor
Data can be lost if the data length is not the same for both
master and slave devices.
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Preliminary
Note
Chapter 12 Queued Serial Peripheral Interface (QSPI)
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