MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 65

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2.3.11 ADC Limit Status Register (ADC_LIMSTAT)
The limit status register latches in the result of the comparison between the result of the
sample and the respective limit register, HILIM0-7and LOLIM0-7. Here is an example: If
the result for the channel programmed in CLIST1[SAMPLE0] is greater than the value
programmed into the High Limit Register zero, then the LIMSTAT[HLS0] bit is set to
one. An interrupt is generated if the CTRL1[HLMTIE] bit is set. A bit may only be
cleared by writing a value of one to that specific bit. These bits are sticky. Once set, the
bits require a specific modification to clear them. They are not cleared automatically by
subsequent conversions.
Address: ADC_LIMSTAT – F080h base + Ah offset = F08Ah
2.3.12 ADC Zero Crossing Status Register (ADC_ZXSTAT)
Address: ADC_ZXSTAT – F080h base + Bh offset = F08Bh
Freescale Semiconductor
Reset
Reset
Read
Read
Write
Write
Bit
Bit
Reserved
HLS[7:0]
LLS[7:0]
15–8
15–8
Field
Field
7–0
15
15
0
0
14
14
0
0
High Limit Status Bits
Low Limit Status Bits
This read-only bitfield is reserved and always has the value zero.
13
13
0
0
12
12
HLS[7:0]
0
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
0
ADC_LIMSTAT field descriptions
11
11
0
0
ADC_ZXSTAT field descriptions
Table continues on the next page...
10
10
0
0
0
0
9
9
Preliminary
0
0
8
8
Description
Description
0
0
7
7
0
0
6
6
Chapter 2 Analog-to-Digital Converter (ADC)
0
0
5
5
ZCS[7:0]
0
0
4
LLS[7:0]
4
0
0
3
3
0
0
2
2
0
0
1
1
0
0
0
0
65