MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 591

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 19 Cyclic Redundancy Check Generator (CRC)
19.4 Functional Description
To enable the CRC function, a write to the CRCH register will trigger the first half of the
seed mechanism which will place the CRCH value directly into bits 15-8 of the CRC
generator shift register. The CRC generator will then expect a write to CRCL to complete
the seed mechanism.
As soon as the CRCL register is written to, its value will be loaded directly into bits 7-0
of the shift register, and the second half of the seed mechanism will be complete. This
value in CRCH:CRCL will be the initial seed value in the CRC generator.
Now the first byte of the data on which the CRC calculation will be applied should be
written to CRCL. This write after the completion of the seed mechanism will trigger the
CRC module to begin the CRC checking process. The CRC generator will shift the bits in
the CRCL register (MSB first) into the shift register of the generator. One Bus cycle after
writing to CRCL all 8 bits have been shifted into the CRC generator, and then the result
of the shifting, or the value currently in the shift register, can be read directly from
CRCH:CRCL, and the next data byte to include in the CRC calculation can be written to
the CRCL register.
This next byte will then also be shifted through the CRC generator's 16-bit shift register,
and after the shifting has been completed, the result of this second calculation can be read
directly from CRCH:CRCL.
After each byte has finished shifting, a new CRC result will appear in CRCH:CRCL, and
an additional byte may be written to the CRCL register to be included within the CRC16-
CCITT calculation. A new CRC result will appear in CRCH:CRCL each time 8-bits have
been shifted into the shift register.
To start a new CRC calculation, write to CRCH, and the seed mechanism for a new CRC
calculation will begin again.
19.4.1 ITU-T (CCITT) Recommendations and Expected CRC
Results
16
12
5
The CRC polynomial 0x1021 (x
+ x
+ x
+ 1) is popularly known as CRC-CCITT
since it was initially proposed by the ITU-T (formerly CCITT) committee.
Although the ITU-T recommendations are very clear about the polynomial to be used,
0x1021, they accept variations in the way the polynomial is implemented:
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Preliminary
Freescale Semiconductor
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