MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 63

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
Reserved
EOSI1
EOSI0
LLMTI
CIP1
Field
ZCI
14
13
12
11
10
9
This bit indicates whether a scan is in progress. This refers to any scan except a B converter scan in non-
simultaneous parallel scan modes.
0
1
Conversion in Progress
This bit indicates whether a scan is in progress. This refers only to a B converter scan in non-
simultaneous parallel scan modes.
0
1
This read-only bit is reserved and always has the value zero.
End of Scan Interrupt
This bit indicates whether a scan of analog inputs have been completed since the last read of the status
register or since a reset. This bit is cleared by writing a one to it. This bit cannot be set by software.
In looping scan modes, this interrupt is triggered at the completion of each iteration of the loop.
This interrupt is triggered only by the completion of a B converter scan in non-simultaneous parallel scan
modes.
0
1
End of Scan Interrupt
This bit indicates whether a scan of analog inputs have been completed since the last read of the status
register or since a reset. This bit is cleared by writing a one to it. This bit cannot be set by software.
STAT[EOSI0] is the preferred bit to poll for scan completion if interrupts are not enabled.
In looping scan modes, this interrupt is triggered at the completion of each iteration of the loop.
This interrupt is triggered upon the completion of any scan except for the completion of a B converter
scan in non-simultaneous parallel scan modes.
0
1
Zero Crossing Interrupt
If the respective offset register is configured by having a value greater than 0000h, zero crossing checking
is enabled. If the offset register is programmed with 7FF8h, the result will always be less than or equal to
zero. On the other hand, if 0000h is programmed into the offset register, the result will always be greater
than or equal to zero, and no zero crossing can occur because the sign of the result will not change. This
interrupt asserts at the completion of an individual conversion which may or may not be the end of a scan.
This bit is cleared by writing a "1" to all active ZXSTAT[ZCS] bits.
0
1
Low Limit Interrupt
Idle state
A scan cycle is in progress. The ADC will ignore all sync pulses or start commands
Idle state
A scan cycle is in progress. The ADC will ignore all sync pulses or start commands
A scan cycle has not been completed, no end of scan IRQ pending
A scan cycle has been completed, end of scan IRQ pending
A scan cycle has not been completed, no end of scan IRQ pending
A scan cycle has been completed, end of scan IRQ pending
No zero crossing interrupt request
Zero crossing encountered, IRQ pending if CTRL1[ZCIE] is set
ADC_STAT field descriptions (continued)
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Table continues on the next page...
Preliminary
Description
Chapter 2 Analog-to-Digital Converter (ADC)
63