MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 79

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2.3.23 ADC Power Control Register (ADC_PWR2)
Address: ADC_PWR2 – F080h base + 39h offset = F0B9h
2.4 Functional Description
The ADC consists of two eight-channel input select functions, which are two independent
sample and hold (S/H) circuits feeding two separate 12-bit ADCs. The two separate
converters store their results in an accessible buffer, awaiting further processing.
Freescale Semiconductor
Reset
Read
Write
Bit
Reserved
Reserved
DIV1[4:0]
SPEEDB
SPEEDA
15–13
12–8
Field
7–4
3–2
1–0
15
0
14
0
0
This read-only bitfield is reserved and always has the value zero.
Clock Divisor Select
The divider circuit operates in the same manner as the CTRL2[DIV0] field but is used to generate the
clock used by ADCB during parallel non-simultaneous scan modes.
This read-only bitfield is reserved and always has the value zero.
ADCB Speed Control Bits
These bits configure the clock speed at which the ADCB can operate. Faster conversion speeds require
greater current consumption.
00
01
10
11
ADCA Speed Control Bits
These bits configure the clock speed at which the ADCA can operate. Faster conversion speeds require
greater current consumption.
00
01
10
11
13
Conversion clock frequency ≤ 5 MHz
Conversion clock frequency ≤ 12 MHz
Conversion clock frequency ≤ 15 MHz
Reserved. Setting SPEEDB to this value will lead to unexpected current consumption by the
converters and should be avoided.
Conversion clock frequency ≤ 5 MHz
Conversion clock frequency ≤ 12 MHz
Conversion clock frequency ≤ 15 MHz
Reserved. Setting SPEEDA to this value will lead to unexpected current consumption by the
converters and should be avoided.
0
12
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
11
0
ADC_PWR2 field descriptions
DIV1[4:0]
10
0
1
9
Preliminary
0
8
Description
0
7
0
6
Chapter 2 Analog-to-Digital Converter (ADC)
0
0
5
0
4
SPEEDB
0
3
0
2
SPEEDA
0
1
0
0
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