MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 368

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Functional Description
11.4.3.3 Break Characters
Writing a logic one to the send break bit, CTRL1[SBK], loads the transmit shift register
with a break character. A break character contains all logic zeroes and has no start, stop,
or parity bit. Break character length depends on CTRL1[M]. As long as CTRL1[SBK] is
at logic one, transmitter logic continuously loads break characters into the transmit shift
register. After software clears CTRL1[SBK], the shift register finishes transmitting the
last break character and then transmits at least one logic one. The automatic logic one at
the end of the last break character guarantees the recognition of the start bit of the next
frame.
The SCI recognizes a break character when a start bit is followed by eight or nine logic
zero data bits and a logic zero where the stop bit should be. Receiving a break character
has these effects on SCI registers:
11.4.3.4 Preambles
A preamble contains all logic ones and has no start, stop, or parity bit. Preamble length
depends on CTRL1[M]. The preamble is a synchronizing mechanism that begins the first
transmission initiated after writing CTRL1[TE] from 0 to 1.
If CTRL1[TE] is cleared during a transmission, the TXD pin becomes idle after
completion of the transmission in progress. Clearing and then setting CTRL1[TE] during
a transmission queues a preamble to be sent after the frame currently being transmitted.
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• Sets the framing error flag, STAT[FE]
• Sets the receive data register full flag, STAT[RDRF], if CTRL2[RFWM] = 00
• Clears the SCI data register
• May set the overrun flag (STAT[OR]), noise flag (STAT[NF]), parity error flag
(STAT[PF]), or receiver active flag (STAT[RAF])
Toggle CTRL1[TE] for a queued preamble when STAT[TDRE]
becomes set and immediately before writing the next character
to the DATA register.
When queueing a preamble, return CTRL1[TE] to logic one
before the stop bit of the current frame shifts out to the TXD
pin. Setting CTRL1[TE] after the stop bit appears on TXD
causes data previously written to the SCI data register to be
lost.
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Preliminary
Note
Freescale Semiconductor